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[23.128.96.18]) by mx.google.com with ESMTP id v5si2433026ejv.698.2021.06.09.06.25.13; Wed, 09 Jun 2021 06:25:38 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236929AbhFIHDo (ORCPT + 99 others); Wed, 9 Jun 2021 03:03:44 -0400 Received: from mail-vs1-f44.google.com ([209.85.217.44]:43748 "EHLO mail-vs1-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233367AbhFIHDn (ORCPT ); Wed, 9 Jun 2021 03:03:43 -0400 Received: by mail-vs1-f44.google.com with SMTP id s22so12305917vsl.10; Wed, 09 Jun 2021 00:01:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=nPGO9/KeQ6w5z6ANe/Ck93Gtpb7H7AIw4HClfuQsFoo=; b=gfUfk/M9ZiaEH6d00jzUW5HkxmUYg+9z12QXae0gpi9LhvI8iYZglgL7TGOxkbWRwY 1A1zd5vzyHjTaaNcwwFic6wBsbUxcCqPGW/NWzHRRJnJ1U5jpXCXXC8m2B7jSRQx4UD0 YHimnYnkYLOOZysuMZVuXG3tpj7rD5NzhQkkANaPbZwUWblCx9C999A5BRekBQLrckuV j6mMe2hDMgnl8mVqMOGy3jvtQyxeDRir5GoXaowfZnGzlucD2NAf69JwWS17BO4rvZQt aICZ96Su9FNwszMjC0vhGnuqMjT0MCwdc1IG7EGDMEyTh3RLn3aU2JnCOxmSu0oXru76 CgOQ== X-Gm-Message-State: AOAM5310ClW0Vh+5aEeBYaRFT5z/qy0I7uIWYca1SiqvQppIzakhodP8 rAaOYBkmNH0pgp5eYLFJpOgrS8+6OHZjUu4qt28= X-Received: by 2002:a05:6102:c4c:: with SMTP id y12mr3842919vss.18.1623222093214; Wed, 09 Jun 2021 00:01:33 -0700 (PDT) MIME-Version: 1.0 References: <20210603221758.10305-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20210603221758.10305-12-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: From: Geert Uytterhoeven Date: Wed, 9 Jun 2021 09:01:21 +0200 Message-ID: Subject: Re: [PATCH v2 11/12] arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's To: Biju Das Cc: Prabhakar Mahadev Lad , Magnus Damm , Rob Herring , Michael Turquette , Stephen Boyd , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Jiri Slaby , Philipp Zabel , "linux-renesas-soc@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-clk@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-serial@vger.kernel.org" , Prabhakar Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Biju, On Fri, Jun 4, 2021 at 3:55 PM Biju Das wrote: > > Subject: [PATCH v2 11/12] arm64: dts: renesas: Add initial DTSI for > > RZ/G2{L,LC} SoC's > > > > Add initial DTSI for RZ/G2{L,LC} SoC's. > > > > File structure: > > r9a07g044.dtsi => RZ/G2L family SoC common parts r9a07g044l1.dtsi => > > Specific to RZ/G2L (R9A07G044L single cortex A55) SoC > > > > Signed-off-by: Lad Prabhakar > > Signed-off-by: Biju Das > > --- /dev/null > > +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > > + cpg: clock-controller@11010000 { > > + compatible = "renesas,r9a07g044-cpg"; > > + reg = <0 0x11010000 0 0x10000>; > > What about WDTOVF_RST(0xB10) and WDTRST_SEL(0xB14) registers, this registers to be handled by WDT driver. > Unfortunately it is in CPG block. > > So do we need to map the entire CPG registers or up to 0xB00? > > Geert, Prabhakar: Any thoughts? As the registers are part of the CPG block, I think they should be covered by the CPG node. You can handle them in the CPG driver, through functions called from the WDT driver (cfr. rcar_rst_read_mode_pins()). Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds