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[23.128.96.18]) by mx.google.com with ESMTP id l15si202426ejc.521.2021.06.09.09.36.18; Wed, 09 Jun 2021 09:36:42 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236014AbhFIQAH (ORCPT + 99 others); Wed, 9 Jun 2021 12:00:07 -0400 Received: from mail-vs1-f51.google.com ([209.85.217.51]:38700 "EHLO mail-vs1-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233575AbhFIQAG (ORCPT ); Wed, 9 Jun 2021 12:00:06 -0400 Received: by mail-vs1-f51.google.com with SMTP id x8so195194vso.5; Wed, 09 Jun 2021 08:57:55 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=eoJtWHTY9D4MPvxk9n7gKkmyyHPN7V7mUcBlJqd6sSw=; b=gV6gsG8fnD2VmrscSXDkwgr6X11r0JcTZZL2PhQMo9KBPW0uIDJYVb+GuU2G+ZTb5W LOeypJCWLM90kccZ36psVfnEV7bWLpBarNMX5aun+zw6gtdQf2T+vDLq5EtpVRlvuV8z vweqG6aSQyCKHu4RAs1sNZXclJSYKVl8kTY99jGZ3lWc3p6N68S7GAIw7y41wQnuxTj6 Hv2xhWBEktN6dnfOEEKQLwfd26rXrPnoY7HyWWP+9Ed/zsvlZEPirKDEeVXMvj3uQG2v tZD8hyx2QyphU6Z3GvlUIG0eXimL+oJFxmISxTcxuf8Dpei0x9wxLOWH63imPIr0b0tg 8UkA== X-Gm-Message-State: AOAM532KU3AbBtt7CRDFFd1tkTQdQ6k7AUO3la7eEbJEUczAqX6j4P5i etPYOY/y8iZid9wmayyd1dMePG2p80hnzDwgjlc= X-Received: by 2002:a67:3c2:: with SMTP id 185mr927502vsd.42.1623254275141; Wed, 09 Jun 2021 08:57:55 -0700 (PDT) MIME-Version: 1.0 References: <20210604180933.16754-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20210604180933.16754-3-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: From: Geert Uytterhoeven Date: Wed, 9 Jun 2021 17:57:43 +0200 Message-ID: Subject: Re: [PATCH 2/3] soc: renesas: Add support to read LSI DEVID register of RZ/G2{L,LC} SoC's To: "Lad, Prabhakar" Cc: Lad Prabhakar , Magnus Damm , Rob Herring , Linux-Renesas , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Linux Kernel Mailing List , Biju Das Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Prabhakar, On Wed, Jun 9, 2021 at 5:50 PM Lad, Prabhakar wrote: > On Wed, Jun 9, 2021 at 8:27 AM Geert Uytterhoeven wrote: > > On Fri, Jun 4, 2021 at 8:09 PM Lad Prabhakar > > wrote: > > > Add support for reading the LSI DEVID register which is present in > > > SYSC block of RZ/G2{L,LC} SoC's. > > > > > > Signed-off-by: Lad Prabhakar > > > Reviewed-by: Biju Das > > > > Thanks for your patch! > > > > > --- a/drivers/soc/renesas/renesas-soc.c > > > +++ b/drivers/soc/renesas/renesas-soc.c > > > @@ -56,6 +56,11 @@ static const struct renesas_family fam_rzg2 __initconst __maybe_unused = { > > > .reg = 0xfff00044, /* PRR (Product Register) */ > > > }; > > > > > > +static const struct renesas_family fam_rzg2l __initconst __maybe_unused = { > > > + .name = "RZ/G2L", > > > + .reg = 0x11020a04, > > > > Please don't add hardcoded register addresses for new SoCs (i.e. drop > > ".reg"). The "renesas,r9a07g044-sysc" is always present. > > And if it were missing, the hardcoded fallback would lead into the > > classic CCCR/PRR scheme, which is not correct for RZ/G2L... > > > I wanted to avoid iomap for the entire sysc block for just a single register. The mapping will be rounded up to PAGE_SIZE anyway (I know, SYSC is 64 KiB, hence larger than the typical page size). Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds