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Date:   Wed, 9 Jun 2021 09:52:40 +0200
From:   Marco Felsch <m.felsch@pengutronix.de>
To:     Martin Kepplinger <martin.kepplinger@puri.sm>
Cc:     festevam@gmail.com, krzk@kernel.org,
        laurent.pinchart@ideasonboard.com, devicetree@vger.kernel.org,
        kernel@pengutronix.de, kernel@puri.sm,
        linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com,
        linux-kernel@vger.kernel.org, linux-media@vger.kernel.org,
        linux-staging@lists.linux.dev, mchehab@kernel.org,
        phone-devel@vger.kernel.org, robh@kernel.org, shawnguo@kernel.org,
        slongerbeam@gmail.com
Subject: Re: [PATCH v3 3/3] arm64: dts: imx8mq: add mipi csi phy and csi
 bridge descriptions
Message-ID: <20210609075240.ajx6ejvqie4sgkvj@pengutronix.de>
References: <20210608104128.1616028-1-martin.kepplinger@puri.sm>
 <20210608104128.1616028-4-martin.kepplinger@puri.sm>
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In-Reply-To: <20210608104128.1616028-4-martin.kepplinger@puri.sm>
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Hi Martin,

On 21-06-08 12:41, Martin Kepplinger wrote:

...

> +			csi1: csi@30a90000 {
> +				compatible = "fsl,imx7-csi";

AFAIK an unwritten rule (at least for the iMX mach) is to specify the
SoC specific compatible and the compatible which is supported by the
driver already, so this should be:

compatible = "fsl,imx8mq-csi", "fsl,imx7-csi";

This is very helpful if we need to handle some quirk for the imx8mq
later on.

Regards,
  Marco


> +				reg = <0x30a90000 0x10000>;
> +				interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk IMX8MQ_CLK_CSI1_ROOT>;
> +				clock-names = "mclk";
> +				status = "disabled";
> +
> +				port {
> +					csi1_ep: endpoint {
> +						remote-endpoint = <&csi1_mipi_ep>;
> +					};
> +				};
> +			};
> +
> +			mipi_csi2: csi@30b60000 {
> +				compatible = "fsl,imx8mq-mipi-csi2";
> +				reg = <0x30b60000 0x1000>;
> +				clocks = <&clk IMX8MQ_CLK_CSI2_CORE>,
> +				   <&clk IMX8MQ_CLK_CSI2_ESC>,
> +				   <&clk IMX8MQ_CLK_CSI2_PHY_REF>,
> +				   <&clk IMX8MQ_CLK_CLKO2>;
> +				clock-names = "core", "esc", "pxl", "clko2";
> +				assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE>,
> +				    <&clk IMX8MQ_CLK_CSI2_PHY_REF>,
> +				    <&clk IMX8MQ_CLK_CSI2_ESC>;
> +				assigned-clock-rates = <266000000>, <333000000>, <66000000>;
> +				assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
> +					<&clk IMX8MQ_SYS2_PLL_1000M>,
> +					<&clk IMX8MQ_SYS1_PLL_800M>;
> +				power-domains = <&pgc_mipi_csi2>;
> +				reset = <&src>;
> +				phy = <&iomuxc_gpr>;
> +				interconnects = <&noc IMX8MQ_ICM_CSI2 &noc IMX8MQ_ICS_DRAM>;
> +				interconnect-names = "dram";
> +				status = "disabled";
> +
> +				ports {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +
> +					port@0 {
> +						reg = <0>;
> +
> +						csi2_mipi_ep: endpoint {
> +							remote-endpoint = <&csi2_ep>;
> +						};
> +					};
> +				};
> +			};
> +
> +			csi2: csi@30b80000 {
> +				compatible = "fsl,imx7-csi";
> +				reg = <0x30b80000 0x10000>;
> +				interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk IMX8MQ_CLK_CSI2_ROOT>;
> +				clock-names = "mclk";
> +				status = "disabled";
> +
> +				port {
> +					csi2_ep: endpoint {
> +						remote-endpoint = <&csi2_mipi_ep>;
> +					};
> +				};
> +			};
> +
>  			mu: mailbox@30aa0000 {
>  				compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu";
>  				reg = <0x30aa0000 0x10000>;
> -- 
> 2.30.2
> 
> 
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> 

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