Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
MIME-Version: 1.0
References: <20210604180933.16754-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <20210604180933.16754-3-prabhakar.mahadev-lad.rj@bp.renesas.com> <CAMuHMdVkKhD3kU-DtPzrGfNf4Sn5Ht09Z1N0scwx1XJoG-F6Mg@mail.gmail.com>
In-Reply-To: <CAMuHMdVkKhD3kU-DtPzrGfNf4Sn5Ht09Z1N0scwx1XJoG-F6Mg@mail.gmail.com>
From:   "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Date:   Wed, 9 Jun 2021 16:49:34 +0100
Message-ID: <CA+V-a8tOMtS59OoWVK-c=zy2iK_nv_16Xu+2DBcUQPTq7nCa1Q@mail.gmail.com>
Subject: Re: [PATCH 2/3] soc: renesas: Add support to read LSI DEVID register
 of RZ/G2{L,LC} SoC's
To:     Geert Uytterhoeven <geert@linux-m68k.org>
Cc:     Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
        Magnus Damm <magnus.damm@gmail.com>,
        Rob Herring <robh+dt@kernel.org>,
        Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@vger.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Biju Das <biju.das.jz@bp.renesas.com>
Content-Type: text/plain; charset="UTF-8"
Precedence: bulk

Hi Geert,

Thank you for the review.

On Wed, Jun 9, 2021 at 8:27 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Fri, Jun 4, 2021 at 8:09 PM Lad Prabhakar
> <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > Add support for reading the LSI DEVID register which is present in
> > SYSC block of RZ/G2{L,LC} SoC's.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/drivers/soc/renesas/renesas-soc.c
> > +++ b/drivers/soc/renesas/renesas-soc.c
> > @@ -56,6 +56,11 @@ static const struct renesas_family fam_rzg2 __initconst __maybe_unused = {
> >         .reg    = 0xfff00044,           /* PRR (Product Register) */
> >  };
> >
> > +static const struct renesas_family fam_rzg2l __initconst __maybe_unused = {
> > +       .name   = "RZ/G2L",
> > +       .reg    = 0x11020a04,
>
> Please don't add hardcoded register addresses for new SoCs (i.e. drop
> ".reg").  The "renesas,r9a07g044-sysc" is always present.
> And if it were missing, the hardcoded fallback would lead into the
> classic CCCR/PRR scheme, which is not correct for RZ/G2L...
>
I wanted to avoid iomap for the entire sysc block for just a single register.

> > @@ -348,6 +361,25 @@ static int __init renesas_soc_init(void)
> >                 goto done;
> >         }
> >
> > +       np = of_find_compatible_node(NULL, NULL, "renesas,r9a07g044-sysc");
> > +       if (np) {
> > +               of_node_put(np);
> > +               chipid = ioremap(family->reg, 4);
>
> Just use of_iomap(np, 0)...
>
will do.

> > +
> > +               if (chipid) {
> > +                       product = readl(chipid);
>
> ... and add the DEVID offset within the SYSC block here.
>
will do.

Cheers,
Prabhakar

> > +                       iounmap(chipid);
> > +
> > +                       if (soc->id && (product & 0xfffffff) != soc->id) {
> > +                               pr_warn("SoC mismatch (product = 0x%x)\n",
> > +                                       product);
> > +                               return -ENODEV;
> > +                       }
> > +               }
> > +
> > +               goto done;
> > +       }
> > +
> >         /* Try PRR first, then hardcoded fallback */
> >         np = of_find_compatible_node(NULL, NULL, "renesas,prr");
> >         if (np) {
>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds