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References: <973add45-9fd2-7abc-3a97-96a26c263ea0@linux.intel.com> <20210609194926.1949859-1-sathyanarayanan.kuppuswamy@linux.intel.com>
In-Reply-To: <20210609194926.1949859-1-sathyanarayanan.kuppuswamy@linux.intel.com>
From:   Dan Williams <dan.j.williams@intel.com>
Date:   Wed, 9 Jun 2021 12:56:25 -0700
Message-ID: <CAPcyv4gQiSLdyXiBB+3zz7=eOX1C0Uuo47846sb675hSZ0GHiQ@mail.gmail.com>
Subject: Re: [RFC v2-fix-v5 1/1] x86: Skip WBINVD instruction for VM guest
To:     Kuppuswamy Sathyanarayanan 
        <sathyanarayanan.kuppuswamy@linux.intel.com>
Cc:     Peter Zijlstra <peterz@infradead.org>,
        Andy Lutomirski <luto@kernel.org>,
        Dave Hansen <dave.hansen@intel.com>,
        Tony Luck <tony.luck@intel.com>,
        Andi Kleen <ak@linux.intel.com>,
        Kirill Shutemov <kirill.shutemov@linux.intel.com>,
        Kuppuswamy Sathyanarayanan <knsathya@kernel.org>,
        Raj Ashok <ashok.raj@intel.com>,
        Sean Christopherson <seanjc@google.com>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Linux ACPI <linux-acpi@vger.kernel.org>,
        "Rafael J. Wysocki" <rjw@rjwysocki.net>
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Precedence: bulk

[ add back linux-acpi and Rafael ]


On Wed, Jun 9, 2021 at 12:49 PM Kuppuswamy Sathyanarayanan
<sathyanarayanan.kuppuswamy@linux.intel.com> wrote:
>
> VM guests that supports ACPI, use standard ACPI mechanisms to
> signal sleep state entry (including reboot) to the host. The
> ACPI specification mandates WBINVD on any sleep state entry
> with the expectation that the platform is only responsible for
> maintaining the state of memory over sleep states, not
> preserving dirty data in any CPU caches. ACPI cache flushing
> requirements pre-date the advent of virtualization. Given guest
> sleep state entry does not affect any host power rails it is not
> required to flush caches. The host is responsible for maintaining
> cache state over its own bare metal sleep state transitions that
> power-off the cache. A TDX guest, unlike a typical guest, will
> machine check if the CPU cache is powered off.

Looks like you are wrapping at column 62 than 72, double check that
for the final submission of this series. Other than that this looks
good to me.

Reviewed-by: Dan Williams <dan.j.williams@intel.com>