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Date:   Thu, 10 Jun 2021 14:03:03 +0200
From:   Thierry Reding <treding@nvidia.com>
To:     Robin Murphy <robin.murphy@arm.com>,
        Krishna Reddy <vdumpa@nvidia.com>
CC:     Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>,
        <linux-arm-msm@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <iommu@lists.linux-foundation.org>, Will Deacon <will@kernel.org>,
        <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH] iommu/io-pgtable-arm: Optimize partial walk flush for
 large scatter-gather list
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On Thu, Jun 10, 2021 at 12:33:56PM +0100, Robin Murphy wrote:
> On 2021-06-10 10:36, Sai Prakash Ranjan wrote:
> > Hi Robin,
> >=20
> > On 2021-06-10 14:38, Robin Murphy wrote:
> > > On 2021-06-10 06:24, Sai Prakash Ranjan wrote:
> > > > Hi Robin,
> > > >=20
> > > > On 2021-06-10 00:14, Robin Murphy wrote:
> > > > > On 2021-06-09 15:53, Sai Prakash Ranjan wrote:
> > > > > > Currently for iommu_unmap() of large scatter-gather list
> > > > > > with page size
> > > > > > elements, the majority of time is spent in flushing of
> > > > > > partial walks in
> > > > > > __arm_lpae_unmap() which is a VA based TLB invalidation (TLBIVA=
 for
> > > > > > arm-smmu).
> > > > > >=20
> > > > > > For example: to unmap a 32MB scatter-gather list with
> > > > > > page size elements
> > > > > > (8192 entries), there are 16->2MB buffer unmaps based on
> > > > > > the pgsize (2MB
> > > > > > for 4K granule) and each of 2MB will further result in
> > > > > > 512 TLBIVAs (2MB/4K)
> > > > > > resulting in a total of 8192 TLBIVAs (512*16) for
> > > > > > 16->2MB causing a huge
> > > > > > overhead.
> > > > > >=20
> > > > > > So instead use io_pgtable_tlb_flush_all() to invalidate
> > > > > > the entire context
> > > > > > if size (pgsize) is greater than the granule size (4K,
> > > > > > 16K, 64K). For this
> > > > > > example of 32MB scatter-gather list unmap, this results
> > > > > > in just 16 ASID
> > > > > > based TLB invalidations or tlb_flush_all() callback
> > > > > > (TLBIASID in case of
> > > > > > arm-smmu) as opposed to 8192 TLBIVAs thereby increasing
> > > > > > the performance of
> > > > > > unmaps drastically.
> > > > > >=20
> > > > > > Condition (size > granule size) is chosen for
> > > > > > io_pgtable_tlb_flush_all()
> > > > > > because for any granule with supported pgsizes, we will
> > > > > > have at least 512
> > > > > > TLB invalidations for which tlb_flush_all() is already
> > > > > > recommended. For
> > > > > > example, take 4K granule with 2MB pgsize, this will
> > > > > > result in 512 TLBIVA
> > > > > > in partial walk flush.
> > > > > >=20
> > > > > > Test on QTI SM8150 SoC for 10 iterations of iommu_{map_sg}/unma=
p:
> > > > > > (average over 10 iterations)
> > > > > >=20
> > > > > > Before this optimization:
> > > > > >=20
> > > > > > =C2=A0=C2=A0=C2=A0=C2=A0 size=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0 iommu_map_sg=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 iommu_unmap
> > > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 4K=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 2.067 us=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0 1.854 us
> > > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 64K=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 9.598 us=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0 8.802 us
> > > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 1M=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 148.890 us=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0 130.718 us
> > > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 2M=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 305.864 us=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0 67.291 us
> > > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 12M=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0 1793.604 us=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 390.8=
38 us
> > > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 16M=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0 2386.848 us=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 518.1=
87 us
> > > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 24M=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0 3563.296 us=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 775.9=
89 us
> > > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 32M=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0 4747.171 us=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 1033.364 us
> > > > > >=20
> > > > > > After this optimization:
> > > > > >=20
> > > > > > =C2=A0=C2=A0=C2=A0=C2=A0 size=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0 iommu_map_sg=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 iommu_unmap
> > > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 4K=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 1.723 us=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0 1.765 us
> > > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 64K=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 9.880 us=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0 8.869 us
> > > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 1M=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 155.364 us=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0 135.223 us
> > > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 2M=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 303.906 us=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0 5.385 us
> > > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 12M=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0 1786.557 us=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
 21.250 us
> > > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 16M=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0 2391.890 us=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
 27.437 us
> > > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 24M=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0 3570.895 us=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
 39.937 us
> > > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 32M=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0 4755.234 us=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
 51.797 us
> > > > > >=20
> > > > > > This is further reduced once the map/unmap_pages()
> > > > > > support gets in which
> > > > > > will result in just 1 tlb_flush_all() as opposed to 16
> > > > > > tlb_flush_all().
> > > > > >=20
> > > > > > Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora=
=2Eorg>
> > > > > > ---
> > > > > > =C2=A0 drivers/iommu/io-pgtable-arm.c | 7 +++++--
> > > > > > =C2=A0 1 file changed, 5 insertions(+), 2 deletions(-)
> > > > > >=20
> > > > > > diff --git a/drivers/iommu/io-pgtable-arm.c
> > > > > > b/drivers/iommu/io-pgtable-arm.c
> > > > > > index 87def58e79b5..c3cb9add3179 100644
> > > > > > --- a/drivers/iommu/io-pgtable-arm.c
> > > > > > +++ b/drivers/iommu/io-pgtable-arm.c
> > > > > > @@ -589,8 +589,11 @@ static size_t
> > > > > > __arm_lpae_unmap(struct arm_lpae_io_pgtable *data,
> > > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0 if (!iopte_leaf(pte, lvl, iop->fmt)) {
> > > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0 /* Also flush any partial walks */
> > > > > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0 io_pgtable_tlb_flush_walk(iop, iova, size,
> > > > > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0 ARM_LPAE_GRANULE(data));
> > > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0 if (size > ARM_LPAE_GRANULE(data))
> > > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 io_pgtable_tlb_flush_all(iop);
> > > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0 else
> > > > >=20
> > > > > Erm, when will the above condition ever not be true? ;)
> > > > >=20
> > > >=20
> > > > Ah right, silly me :)
> > > >=20
> > > > > Taking a step back, though, what about the impact to drivers other
> > > > > than SMMUv2?
> > > >=20
> > > > Other drivers would be msm_iommu.c, qcom_iommu.c which does the same
> > > > thing as arm-smmu-v2 (page based invalidations), then there is
> > > > ipmmu-vmsa.c
> > > > which does tlb_flush_all() for flush walk.
> > > >=20
> > > > > In particular I'm thinking of SMMUv3.2 where the whole
> > > > > range can be invalidated by VA in a single command anyway, so the
> > > > > additional penalties of TLBIALL are undesirable.
> > > > >=20
> > > >=20
> > > > Right, so I am thinking we can have a new generic quirk
> > > > IO_PGTABLE_QUIRK_RANGE_INV
> > > > to choose between range based invalidations(tlb_flush_walk) and
> > > > tlb_flush_all().
> > > > In this case of arm-smmu-v3.2, we can tie up
> > > > ARM_SMMU_FEAT_RANGE_INV with this quirk
> > > > and have something like below, thoughts?
> > > >=20
> > > > if (iop->cfg.quirks & IO_PGTABLE_QUIRK_RANGE_INV)
> > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 io_pgtable_tlb_flu=
sh_walk(iop, iova, size,
> > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ARM_LPAE_GR=
ANULE(data));
> > > > else
> > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 io_pgtable_tlb_flu=
sh_all(iop);
> > >=20
> > > The design here has always been that io-pgtable says *what* needs
> > > invalidating, and we left it up to the drivers to decide exactly
> > > *how*. Even though things have evolved a bit I don't think that has
> > > fundamentally changed - tlb_flush_walk is now only used in this one
> > > place (technically I suppose it could be renamed tlb_flush_table but
> > > it's not worth the churn), so drivers can implement their own
> > > preferred table-invalidating behaviour even more easily than choosing
> > > whether to bounce a quirk through the common code or not. Consider
> > > what you've already seen for the Renesas IPMMU, or SMMUv1 stage 2...
> > >=20
> >=20
> > Thanks for the explanation, makes sense. If I am not mistaken, I see th=
at
> > you are suggesting to move this logic based on size and granule-size to
> > arm-smmu-v2 driver and one more thing below..
>=20
> Simpler than that - following on from my original comment above,
> tlb_flush_walk already knows it's invalidating at least one full level of
> table so there's nothing it even needs to check. Adding a size-based
> heuristic to arm_smmu_inv_range_* for leaf invalidations would be a separ=
ate
> concern (note that changing the non-leaf behaviour might allow cleaning up
> the "reg" indirection there too).
>=20
> > > I'm instinctively a little twitchy about making this a blanket
> > > optimisation for SMMUv2 since I still remember the palaver with our
> > > display and MMU-500 integrations, where it had to implement the dodgy
> > > "prefetch" register to trigger translations before scanning out a
> > > frame since it couldn't ever afford a TLB miss, thus TLBIALL when
> > > freeing an old buffer would be a dangerous hammer to swing. However
> > > IIRC it also had to ensure everything was mapped as 2MB blocks to
> > > guarantee fitting everything in the TLBs in the first place, so I
> > > guess it would still work out OK due to never realistically unmapping
> > > a whole table at once anyway.
> > >=20
> >=20
> > You are also hinting to not do this for all SMMUv2 implementations and =
make
> > it QCOM specific?
>=20
> No, I'm really just wary that the performance implication is more complex
> than a simple unmap latency benefit, possibly even for QCOM. Consider the
> access latency, power and memory bandwidth hit from all the additional
> pagetable walks incurred by other ongoing traffic fighting against those =
16
> successive TLBIASIDs. Whether it's an overall win really depends on the
> specific workload and system conditions as much as the SMMU implementatio=
n.
> Thinking some more, I wonder if the Tegra folks might have an opinion to =
add
> here, given that their multiple-SMMU solution was seemingly about trying =
to
> get enough TLB and pagetable walk bandwidth in the first place?

Yes, so Tegra194 has three different instances of the SMMU. Two of them
are programmed in an interleaved mode to basically double the bandwidth
available. A third instance is specifically reserved for isochronous
memory clients and is used by the display controller to avoid potential
pressure on the dual-SMMU from interfering with display functionality.

I'm not sure if we've ever measured the impact of map/unmap operations
under heavy load. Krishna, do you know if this might be helpful for some
of the use-cases we have on Tegra? Or if it might negatively impact
performance under pressure?

Thierry

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-----END PGP SIGNATURE-----

--um53ZMkAjPcztXZJ--