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From:   Punit Agrawal <punitagrawal@gmail.com>
To:     Marc Zyngier <maz@kernel.org>
Cc:     helgaas@kernel.org, robh+dt@kernel.org,
        linux-rockchip@lists.infradead.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        linux-pci@vger.kernel.org, alexandru.elisei@arm.com, wqu@suse.com,
        robin.murphy@arm.com, pgwipeout@gmail.com, ardb@kernel.org,
        briannorris@chromium.org, shawn.lin@rock-chips.com
Subject: Re: [PATCH v3 0/4] PCI: of: Improvements to handle 64-bit attribute
 for non-prefetchable ranges
References: <20210607112856.3499682-1-punitagrawal@gmail.com>
        <87lf7jqavd.wl-maz@kernel.org>
Date:   Thu, 10 Jun 2021 23:17:26 +0900
In-Reply-To: <87lf7jqavd.wl-maz@kernel.org> (Marc Zyngier's message of "Wed,
        09 Jun 2021 17:08:22 +0100")
Message-ID: <87r1h9kdmx.fsf@stealth>
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Hi Marc,

Marc Zyngier <maz@kernel.org> writes:

> Hi Punit,
>
> On Mon, 07 Jun 2021 12:28:52 +0100,
> Punit Agrawal <punitagrawal@gmail.com> wrote:
>> 
>> Hi,
>> 
>> This is the third iteration to improve handling of the 64-bit
>> attribute on non-prefetchable host bridge ranges. Previous version can
>> be found at [0][1].
>> 
>> This version is a small update over the previous version - changelog
>> below. If there is no futher feedback on the patches, please consider
>> merging them.
>
> Thanks for this. This brings my test machine back to life:
>
> Acked-by: Marc Zyngier <maz@kernel.org>
> Tested-by: Marc Zyngier <maz@kernel.org>

Thanks for taking the patches for a spin. Based on the comments on Patch
1, there'll at least be another update. I'll copy you when I send that
out.

Thanks,
Punit

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