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[23.128.96.18]) by mx.google.com with ESMTP id yh12si3579848ejb.237.2021.06.11.01.05.55; Fri, 11 Jun 2021 01:06:18 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231233AbhFKIDl (ORCPT + 99 others); Fri, 11 Jun 2021 04:03:41 -0400 Received: from mail.kernel.org ([198.145.29.99]:51332 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230188AbhFKIDl (ORCPT ); Fri, 11 Jun 2021 04:03:41 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 9F0CD61027; Fri, 11 Jun 2021 08:01:43 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1lrc6n-006v6z-J1; Fri, 11 Jun 2021 09:01:41 +0100 Date: Fri, 11 Jun 2021 09:01:40 +0100 Message-ID: <87fsxorfrv.wl-maz@kernel.org> From: Marc Zyngier To: Shaokun Zhang Cc: , Wudi Wang , Thomas Gleixner Subject: Re: [PATCH] irqchip/irq-gic-v3-its: Add the checking of ITS version for KVM In-Reply-To: <1623390746-54627-1-git-send-email-zhangshaokun@hisilicon.com> References: <1623390746-54627-1-git-send-email-zhangshaokun@hisilicon.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: zhangshaokun@hisilicon.com, linux-kernel@vger.kernel.org, wangwudi@hisilicon.com, tglx@linutronix.de X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 11 Jun 2021 06:52:26 +0100, Shaokun Zhang wrote: > > From: Wudi Wang > > The version of GIC used by KVM is provided by gic_v3_kvm_info. > The KVM that supports GICv4 or GICv4.1 only checks GIC > version. Actually, the GIC and ITS need to work together. > So we add the checking of ITS version for KVM: If and only if > both GIC & ITS support GICv4, gic_kvm_info.has_v4 is true. > If and only if both GIC & ITS support GICv4.1, > gic_kvm_info.has_v4_1 is true. > > Cc: Thomas Gleixner > Cc: Marc Zyngier > Signed-off-by: Wudi Wang > Signed-off-by: Shaokun Zhang > --- > drivers/irqchip/irq-gic-common.h | 2 ++ > drivers/irqchip/irq-gic-v3-its.c | 3 +++ > drivers/irqchip/irq-gic-v3.c | 10 +++++----- > 3 files changed, 10 insertions(+), 5 deletions(-) > > diff --git a/drivers/irqchip/irq-gic-common.h b/drivers/irqchip/irq-gic-common.h > index ccba8b0fe0f5..e5d44998445a 100644 > --- a/drivers/irqchip/irq-gic-common.h > +++ b/drivers/irqchip/irq-gic-common.h > @@ -10,6 +10,8 @@ > #include > #include > > +extern struct gic_kvm_info gic_v3_kvm_info; > + > struct gic_quirk { > const char *desc; > const char *compatible; > diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c > index 2e6923c2c8a8..45d6163c14d5 100644 > --- a/drivers/irqchip/irq-gic-v3-its.c > +++ b/drivers/irqchip/irq-gic-v3-its.c > @@ -5419,6 +5419,9 @@ int __init its_init(struct fwnode_handle *handle, struct rdists *rdists, > has_v4_1 |= is_v4_1(its); > } > > + gic_v3_kvm_info.has_v4 = has_v4; > + gic_v3_kvm_info.has_v4_1 = has_v4_1; If you are going down that road: what if you have multiple ITSs, implementing a variety of v3, v4, v4.1? We currently support this to some extent, but this is breaking it. What case are you exactly trying to fix? > + > /* Don't bother with inconsistent systems */ > if (WARN_ON(!has_v4_1 && rdists->has_rvpeid)) > rdists->has_rvpeid = false; > diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c > index 37a23aa6de37..7454f99bf580 100644 > --- a/drivers/irqchip/irq-gic-v3.c > +++ b/drivers/irqchip/irq-gic-v3.c > @@ -103,7 +103,7 @@ EXPORT_SYMBOL(gic_nonsecure_priorities); > /* ppi_nmi_refs[n] == number of cpus having ppi[n + 16] set as NMI */ > static refcount_t *ppi_nmi_refs; > > -static struct gic_kvm_info gic_v3_kvm_info; > +struct gic_kvm_info gic_v3_kvm_info; This will conflict with the rework that is in -next, and maybe cause some lifetime issue (see how the structure is now tagged __initdata). > static DEFINE_PER_CPU(bool, has_rss); > > #define MPIDR_RS(mpidr) (((mpidr) & 0xF0UL) >> 4) > @@ -1850,8 +1850,8 @@ static void __init gic_of_setup_kvm_info(struct device_node *node) > if (!ret) > gic_v3_kvm_info.vcpu = r; > > - gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; > - gic_v3_kvm_info.has_v4_1 = gic_data.rdists.has_rvpeid; > + gic_v3_kvm_info.has_v4 &= gic_data.rdists.has_vlpis; > + gic_v3_kvm_info.has_v4_1 &= gic_data.rdists.has_rvpeid; > gic_set_kvm_info(&gic_v3_kvm_info); > } > > @@ -2166,8 +2166,8 @@ static void __init gic_acpi_setup_kvm_info(void) > vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; > } > > - gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; > - gic_v3_kvm_info.has_v4_1 = gic_data.rdists.has_rvpeid; > + gic_v3_kvm_info.has_v4 &= gic_data.rdists.has_vlpis; > + gic_v3_kvm_info.has_v4_1 &= gic_data.rdists.has_rvpeid; > gic_set_kvm_info(&gic_v3_kvm_info); > } Thanks, M. -- Without deviation from the norm, progress is not possible.