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References: <20210612034042.3043112-1-palmer@dabbelt.com>
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From:   Anup Patel <anup@brainfault.org>
Date:   Sat, 12 Jun 2021 10:12:24 +0530
Message-ID: <CAAhSdy2oYbSa_c4cqaHcXKiMagOK9NB4F8stBM=cwi6hfAAHBA@mail.gmail.com>
Subject: Re: [PATCH] RISC-V: Use asm-generic for {in,out}{bwlq}
To:     Palmer Dabbelt <palmer@dabbelt.com>
Cc:     linux-riscv <linux-riscv@lists.infradead.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Atish Patra <Atish.Patra@wdc.com>,
        "linux-kernel@vger.kernel.org List" <linux-kernel@vger.kernel.org>,
        kernel-team@android.com, Palmer Dabbelt <palmerdabbelt@google.com>
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On Sat, Jun 12, 2021 at 9:25 AM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>
> From: Palmer Dabbelt <palmerdabbelt@google.com>
>
> The asm-generic implementation is functionally identical to the RISC-V
> version.
>
> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>

Indeed, these are same as asm-generic.

Reviewed-by: Anup Patel <anup@brainfault.org>

Regards,
Anup

> ---
>  arch/riscv/include/asm/io.h | 13 -------------
>  1 file changed, 13 deletions(-)
>
> diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
> index c025a746a148..69605a474270 100644
> --- a/arch/riscv/include/asm/io.h
> +++ b/arch/riscv/include/asm/io.h
> @@ -52,19 +52,6 @@
>  #define __io_pbw()     __asm__ __volatile__ ("fence iow,o" : : : "memory");
>  #define __io_paw()     __asm__ __volatile__ ("fence o,io"  : : : "memory");
>
> -#define inb(c)         ({ u8  __v; __io_pbr(); __v = readb_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; })
> -#define inw(c)         ({ u16 __v; __io_pbr(); __v = readw_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; })
> -#define inl(c)         ({ u32 __v; __io_pbr(); __v = readl_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; })
> -
> -#define outb(v,c)      ({ __io_pbw(); writeb_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); })
> -#define outw(v,c)      ({ __io_pbw(); writew_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); })
> -#define outl(v,c)      ({ __io_pbw(); writel_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); })
> -
> -#ifdef CONFIG_64BIT
> -#define inq(c)         ({ u64 __v; __io_pbr(); __v = readq_cpu((void*)(c)); __io_par(__v); __v; })
> -#define outq(v,c)      ({ __io_pbw(); writeq_cpu((v),(void*)(c)); __io_paw(); })
> -#endif
> -
>  /*
>   * Accesses from a single hart to a single I/O address must be ordered.  This
>   * allows us to use the raw read macros, but we still need to fence before and
> --
> 2.32.0.272.g935e593368-goog
>