Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
Date:   Sun, 13 Jun 2021 08:44:47 +0800
From:   Jisheng Zhang <jszhang3@mail.ustc.edu.cn>
To:     Palmer Dabbelt <palmer@dabbelt.com>
Cc:     emil.renner.berthing@gmail.com, alex@ghiti.fr,
        Paul Walmsley <paul.walmsley@sifive.com>,
        aou@eecs.berkeley.edu, jszhang@kernel.org,
        Christoph Hellwig <hch@infradead.org>, zong.li@sifive.com,
        anup@brainfault.org, linux-riscv@lists.infradead.org,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 1/4] riscv: Remove CONFIG_PHYS_RAM_BASE_FIXED
Message-ID: <20210613084447.6db3cc02@xhacker>
In-Reply-To: <mhng-dfabeabd-e6df-4035-a9d0-c16269390120@palmerdabbelt-glaptop>
References: <CANBLGcy3HrnmrweSpnDZViVstoWJYh4sCBoaX_24AsgWd=Q9XA@mail.gmail.com>
        <mhng-dfabeabd-e6df-4035-a9d0-c16269390120@palmerdabbelt-glaptop>
MIME-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: 7bit
Precedence: bulk

On Sat, 12 Jun 2021 17:23:51 -0700 (PDT)
Palmer Dabbelt <palmer@dabbelt.com> wrote:

> On Sat, 12 Jun 2021 16:23:03 PDT (-0700), emil.renner.berthing@gmail.com wrote:
> > On Fri, 4 Jun 2021 at 13:51, Alexandre Ghiti <alex@ghiti.fr> wrote:  
> >>
> >> Make the physical RAM base address available for all kernels, not only
> >> XIP kernels as it will allow to simplify address conversions macros.  
> >
> > Am I just reading it wrong or won't this patch make it so that the same kernel
> > can't run on two chips with physical ram starting at different addresses?

I mentioned this point in http://lists.infradead.org/pipermail/linux-riscv/2021-June/006840.html  

> 
> IIUC we were in that position, at least without relocatable kernels.  
> Maybe I'm misunderstanding this, though?

Just my humble opinion, before this series patch, at least geneirc Image
for RV64 + MMU + !XIP is doable.

Thanks

> 
> >
> > /Emil
> >  
> >> ---
> >>  arch/riscv/Kconfig | 6 ------
> >>  1 file changed, 6 deletions(-)
> >>
> >> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> >> index b58596b141fc..3d8e7e4bb45c 100644
> >> --- a/arch/riscv/Kconfig
> >> +++ b/arch/riscv/Kconfig
> >> @@ -493,13 +493,8 @@ config STACKPROTECTOR_PER_TASK
> >>         def_bool y
> >>         depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_TLS
> >>
> >> -config PHYS_RAM_BASE_FIXED
> >> -       bool "Explicitly specified physical RAM address"
> >> -       default n
> >> -
> >>  config PHYS_RAM_BASE
> >>         hex "Platform Physical RAM address"
> >> -       depends on PHYS_RAM_BASE_FIXED
> >>         default "0x80000000"
> >>         help
> >>           This is the physical address of RAM in the system. It has to be
> >> @@ -512,7 +507,6 @@ config XIP_KERNEL
> >>         # This prevents XIP from being enabled by all{yes,mod}config, which
> >>         # fail to build since XIP doesn't support large kernels.
> >>         depends on !COMPILE_TEST
> >> -       select PHYS_RAM_BASE_FIXED
> >>         help
> >>           Execute-In-Place allows the kernel to run from non-volatile storage
> >>           directly addressable by the CPU, such as NOR flash. This saves RAM
> >> --
> >> 2.30.2
> >>
> >>
> >> _______________________________________________
> >> linux-riscv mailing list
> >> linux-riscv@lists.infradead.org
> >> http://lists.infradead.org/mailman/listinfo/linux-riscv  
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv