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Date:   Sun, 13 Jun 2021 11:23:04 +0200
From:   Jonathan =?utf-8?Q?Neusch=C3=A4fer?= <j.neuschaefer@gmx.net>
To:     Linus Walleij <linus.walleij@linaro.org>
Cc:     Jonathan =?utf-8?Q?Neusch=C3=A4fer?= <j.neuschaefer@gmx.net>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@vger.kernel.org>, Rob Herring <robh+dt@kernel.org>,
        OpenBMC Maillist <openbmc@lists.ozlabs.org>,
        Tomer Maimon <tmaimon77@gmail.com>,
        Joel Stanley <joel@jms.id.au>,
        linux-kernel <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 3/8] ARM: dts: wpcm450: Add global control registers
 (GCR) node
Message-ID: <YMXOeBWu31LC+23X@latitude>
References: <20210602120329.2444672-1-j.neuschaefer@gmx.net>
 <20210602120329.2444672-4-j.neuschaefer@gmx.net>
 <CACRpkdY7AqcE4CMAdZHR-DfV-3ZCO3h9kYUZoZCUodLQmyyfXw@mail.gmail.com>
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On Fri, Jun 04, 2021 at 10:01:07AM +0200, Linus Walleij wrote:
> On Wed, Jun 2, 2021 at 2:04 PM Jonathan Neusch=C3=A4fer
> <j.neuschaefer@gmx.net> wrote:
>=20
> > The Global Control Registers (GCR) are a block of registers in Nuvoton
> > SoCs that expose misc functionality such as chip model and version
> > information or pinmux settings.
> >
> > This patch adds a GCR node to nuvoton-wpcm450.dtsi in preparation for
> > enabling pinctrl on this SoC.
> >
> > Signed-off-by: Jonathan Neusch=C3=A4fer <j.neuschaefer@gmx.net>
>=20
> As noted I would name this architecture-neutral with
> syscon@...

Will do.


Jonathan Neusch=C3=A4fer

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