Received: by 2002:a05:6a10:206:0:0:0:0 with SMTP id 6csp2554684pxj; Mon, 14 Jun 2021 01:16:29 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwAkVGgTlxVvdQAPXFKwRrHI+BWY658t6fFJTxOXwRWNdrd0m4gwmfrQ4U6akkSFFbvCePe X-Received: by 2002:a17:906:fcb5:: with SMTP id qw21mr13887930ejb.57.1623658589569; Mon, 14 Jun 2021 01:16:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1623658589; cv=none; d=google.com; s=arc-20160816; b=azkhLsLW3EoNWYtXFNybp9TAbl3eL4u7L6vjQJJ54ZHGfUnYvE9YZuy3OEu/FD3zHO ytRioyg/2FOsLk4LC5xEXzniz+y4kzhSRJaKRA7s4cRwidweYqMpD3dgyV8yJgIZFtd5 cJK3mzQwGF61VysPEm18F6CD7MWheHJIk0rTCZFWq9yputRM7D78C3BH+leDMVL9thvg Dk9MXlXVkQpg9EwIOF4pqRw4gWOORVAgo8UnNqoSzQ8lrNQ/udu7UWEIO21fiUe1VVVy hsdnqe7W2S32GuAjJ+ssIZ5BiJvhwKBNSCnx2S+ewNSjbPY1KV9pGTukdCDP3SA6FWhs gAOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:subject:message-id:date:from:in-reply-to :references:mime-version:dkim-signature; bh=9fAPXLcMnuwc5kCpl7ATb/uElPSg8emw9lkYjZEn50s=; b=ePFpke5jBB3iK1nAMaKoQm03sbMMBG357zqFxfLu116W26SflZnSDkuTi8zFPThLSw VgiM8Xwtljg7rFW9j/+Aa7HCoNd82qKI2iF0K7g+X5u3DOyIXhyLYsy2nTfqDPsCwh7i cYqJqv3IgoZs331mrXvfVEvRTQ0Mq7GQhlsoFaZhYBW6WG2oeRdQtRYlCMN1pIh7uEzy igSuN9wxX3AqRZzEukfr4eCgAhCe/VhTmxb3zvJM/ipiFc0Af306j161Gt1W0JpvxwHG XwM9VhH4cE0bxbbBLC25iovURc+pbF8Ljl4wdlVPKVoaF63tY3X4K9NWrecDQ/ereRLq H7Rw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CMMB9c9S; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id ce5si9845378ejc.305.2021.06.14.01.16.06; Mon, 14 Jun 2021 01:16:29 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CMMB9c9S; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232528AbhFNIQr (ORCPT + 99 others); Mon, 14 Jun 2021 04:16:47 -0400 Received: from mail-ot1-f54.google.com ([209.85.210.54]:41562 "EHLO mail-ot1-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232530AbhFNIQo (ORCPT ); Mon, 14 Jun 2021 04:16:44 -0400 Received: by mail-ot1-f54.google.com with SMTP id p5-20020a9d45450000b029043ee61dce6bso2936021oti.8 for ; Mon, 14 Jun 2021 01:14:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=9fAPXLcMnuwc5kCpl7ATb/uElPSg8emw9lkYjZEn50s=; b=CMMB9c9SNYcug0m4F1ZbPVi7DUsIGlDUumyOHeO/i8F+E69SBXH2sjS+kqYHIRRbeG Vxe/qqAlajLJuI6RUT0vWrZXQ3yy35DtDIFjP9Lcbjy3DHrXMRRCDb//DIIRPXGAb7Wh XZgRATsp+E5wcEk+EfXi4aX9H5TcaKUiTv7o5gHlTMJxa3QaL8KU1Ozi+8m+7MDgNYmP TvQA8FW+tptGFbQ8nONVbrrtyu6BPjDIyyDrAgiXUvVyQPvi+bLssV3s+ivDEDe6AjZK 5v1YM0Lgt7qYrquhTy7cqd36QDNDQ8LrWvd30MxzNCy30zzAZNn48X8TR+sgYBf1a6Nv Q1yw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=9fAPXLcMnuwc5kCpl7ATb/uElPSg8emw9lkYjZEn50s=; b=YHwZTNZKuNuGCaGH7/ywZusxOOi9JNqS67FyVy1n/vHXksUdprJWi7/6h8xg5BrIfC x+TZaKVv/DmodrAkWFtRk/EFmZvGNkCbW22+NZS2B5TZmnzwU0ldslbjgyXJ88VTEgPm gjPFzXVaeLQquupCyTu7jdrE0GekSVv4TCq3omPMLmdD4wf1FjdutpePN2sPNDO8ddDo KduM3TOJVZbjxnGKAuH2PH88Z5/H/Clxlh+Y0Smb1j19Jk+9H2lLal48ybfNqNZKXn4H 9ehOJ220vh26/7Qm6TMm15a5vMYhprm3eYx2zhxAIXxkvPx30ce3XghfNwIfoNhkMdkQ 9lIQ== X-Gm-Message-State: AOAM533qObfvrR16SBhLa+5p2KX4eOSK55TSqfRRcP0XeyWULsSON06L DIcEoH4u14sxqV1gffBbZCsmpbZLRdvIV0Fh4BVAxA== X-Received: by 2002:a9d:1726:: with SMTP id i38mr11894739ota.51.1623658422212; Mon, 14 Jun 2021 01:13:42 -0700 (PDT) MIME-Version: 1.0 References: <20210607113840.15435-1-bhupesh.sharma@linaro.org> <20210607113840.15435-3-bhupesh.sharma@linaro.org> In-Reply-To: From: Bhupesh Sharma Date: Mon, 14 Jun 2021 13:43:31 +0530 Message-ID: Subject: Re: [PATCH 2/8] dt-bindings: pinctrl: qcom,pmic-gpio: Add compatible for SA8155p-adp To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Linus Walleij , Liam Girdwood , Mark Brown , Vinod Koul , Rob Herring , Andy Gross , devicetree , Linux Kernel Mailing List , "open list:GPIO SUBSYSTEM" , bhupesh.linux@gmail.com Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Bjorn, On Fri, 11 Jun 2021 at 08:21, Bjorn Andersson wrote: > > On Mon 07 Jun 06:38 CDT 2021, Bhupesh Sharma wrote: > > > Add pmic-gpio compatible strings for pmm8155au_1 and pmm8155au_2 pmics > > found on SA8155p-adp board. > > > > Cc: Linus Walleij > > Cc: Liam Girdwood > > Cc: Mark Brown > > Cc: Bjorn Andersson > > Cc: Vinod Koul > > Cc: Rob Herring > > Cc: Andy Gross > > Cc: devicetree@vger.kernel.org > > Cc: linux-kernel@vger.kernel.org > > Cc: linux-gpio@vger.kernel.org > > Cc: bhupesh.linux@gmail.com > > Signed-off-by: Bhupesh Sharma > > --- > > Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt | 5 +++++ > > 1 file changed, 5 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt > > index f6a9760558a6..ee4721f1c477 100644 > > --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt > > +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt > > @@ -27,6 +27,8 @@ PMIC's from Qualcomm. > > "qcom,pm660l-gpio" > > "qcom,pm8150-gpio" > > "qcom,pm8150b-gpio" > > + "qcom,pmm8155au-1-gpio" > > + "qcom,pmm8155au-2-gpio" > > As with the regulator this seems to be a single component. > > > "qcom,pm8350-gpio" > > "qcom,pm8350b-gpio" > > "qcom,pm8350c-gpio" > > @@ -116,6 +118,9 @@ to specify in a pin configuration subnode: > > and gpio8) > > gpio1-gpio12 for pm8150b (holes on gpio3, gpio4, gpio7) > > gpio1-gpio12 for pm8150l (hole on gpio7) > > + gpio1-gpio10 for pmm8155au-1 (holes on gpio2, gpio5, gpio7 > > + and gpio8) > > + gpio1-gpio10 for pmm8155au-2 (holes on gpio2, gpio5, gpio7) > > In the schematics all 10 pins are wired on both of these PMICs, so I > don't think there are holes. Please omit the comment. But if we look at the downstream dts (see [1]), we clearly have holes on gpio 2, 5 and 7 on PMM8155AU_2 whereas if we see [2], we can see PMM8155AU_1 has holes on gpio 2, 5, 7 and 8. As I understand, the schematics mention some optional configurations as well which might not be available depending on the default board configuration. [1]. https://source.codeaurora.org/quic/la/kernel/msm-4.14/tree/arch/arm64/boot/dts/qcom/sa8155-pmic-overlay.dtsi?h=LV.AU.0.1.0.r1-15900-gen3meta.0#n92 [2]. https://source.codeaurora.org/quic/la/kernel/msm-4.14/tree/arch/arm64/boot/dts/qcom/sa8155-pmic-overlay.dtsi?h=LV.AU.0.1.0.r1-15900-gen3meta.0#n36 Regards, Bhupesh > > > gpio1-gpio10 for pm8350 > > gpio1-gpio8 for pm8350b > > gpio1-gpio9 for pm8350c > > -- > > 2.31.1 > >