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Date:   Mon, 14 Jun 2021 10:38:17 +0100
Message-ID: <87a6nsrdkm.wl-maz@kernel.org>
From:   Marc Zyngier <maz@kernel.org>
To:     Anup Patel <anup@brainfault.org>
Cc:     Anup Patel <anup.patel@wdc.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Palmer Dabbelt <palmerdabbelt@google.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Daniel Lezcano <daniel.lezcano@linaro.org>,
        Rob Herring <robh+dt@kernel.org>,
        Atish Patra <atish.patra@wdc.com>,
        Alistair Francis <Alistair.Francis@wdc.com>,
        linux-riscv <linux-riscv@lists.infradead.org>,
        "linux-kernel@vger.kernel.org List" <linux-kernel@vger.kernel.org>,
        DTML <devicetree@vger.kernel.org>
Subject: Re: [RFC PATCH v1 05/10] irqchip: Add ACLINT software interrupt driver
In-Reply-To: <CAAhSdy2e9BsgtTL3ETRC-dvHW9hgKmgRi87Gsk+vUT-kMsJ4NQ@mail.gmail.com>
References: <20210612160422.330705-1-anup.patel@wdc.com>
        <20210612160422.330705-6-anup.patel@wdc.com>
        <878s3et831.wl-maz@kernel.org>
        <CAAhSdy2e9BsgtTL3ETRC-dvHW9hgKmgRi87Gsk+vUT-kMsJ4NQ@mail.gmail.com>
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On Sun, 13 Jun 2021 13:25:40 +0100,
Anup Patel <anup@brainfault.org> wrote:
> 
> On Sun, Jun 13, 2021 at 3:11 PM Marc Zyngier <maz@kernel.org> wrote:
> >
> > I'm sorry, but this really isn't an irqchip driver. This is a piece of
> > arch-specific code that uses *none* of the irq subsystem abstractions
> > apart from the IRQCHIP_DECLARE() macro.
> 
> Yes, I was not sure we can call it IRQCHIP hence the RFC PATCH.
> 
> Both ACLINT MSWI and SSWI are special devices providing only IPI
> support so I will re-think how to fit this.

It depends on how you think of IPIs in your architecture.

arm64 (and even now 32bit) have been moved to a mode where IPIs are
normal interrupts, as it helps with other things such as our pseudo
NMIs, and reduces code duplication. MIPS has done the same for a long
time (they don't have dedicated HW for that).

	M.

-- 
Without deviation from the norm, progress is not possible.