Received: by 2002:a05:6a10:206:0:0:0:0 with SMTP id 6csp2823016pxj; Mon, 14 Jun 2021 08:00:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyUEDbQ/8NwRYpKihTwJefO6jm5g4ZP9NCXP3RaHqyLPfOG5txPvqE3rPHko4vIKpOZxn65 X-Received: by 2002:a05:6402:b17:: with SMTP id bm23mr17338604edb.236.1623682801693; Mon, 14 Jun 2021 08:00:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1623682801; cv=none; d=google.com; s=arc-20160816; b=MZfF84oibt2JySvUDXJ8PURqcfLZSqSf7lkLSshHTWrIFQq6iHFdpFE7nm8EfHo9Ul z6sP+NwZjCBkogCIykTxG9RnDfxfkWe/yscyRamFS1MRPNqpeyis/UmHWd8Uv+YpWp5C /UUpteez/cCJxLKwOQxRpaM0476r5z4GqFUREnXt27b6CtTE8kN8d02KsbxBXPuKbYd0 p2IeMmY7truH/tMs9OdjRDxovEYYaC8dSBoeEjix6FTru0H+rlpQsYN+2fpvmNIBi0Pc RMfI0nruKJ9Vq2VlEWq43ZSOTxaUypkm9S3972GbmgR/Y+Uu4bxXN1W/ZqSnYqBH23Ne YGbQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=uUMW366xxr93Dt8fLVX3VI2V4jd3Mey//z8GyOI8Sac=; b=Yt7s7Uf7LBDkffoxrk0wYqnRd+PG986P2Xw4tAjTQtTau3xqNZRTkY3y4t8BMgTvsN Vy4nJXZHEZvPxO+kbWj96uLGam7SSpBt4Yf+Am5KkjS8v1MFyT5q21IZZpFdJefbo378 EZ/HM3at6K9dNRwf7hIDD4ym4UgUFjIViaXDXfUYvVD3J//vIcnr3RqGtIeDeDThCN4k LsyVA2vjkx9BqdGKfJaniPJEwNX5aw8btBT7WdQlwdR5C4bswV1OEH6tBMYPwQSQsb9c +ILGNI4LpO1okbtKUcUZeG6Ne1tBYgcHSCrpCvgnm+yP2wCS/mkVfhw3KFHG/4Q0FDbv hHUw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id i20si11407396ejo.517.2021.06.14.07.59.38; Mon, 14 Jun 2021 08:00:01 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233110AbhFNO7g (ORCPT + 99 others); Mon, 14 Jun 2021 10:59:36 -0400 Received: from foss.arm.com ([217.140.110.172]:37998 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233087AbhFNO7g (ORCPT ); Mon, 14 Jun 2021 10:59:36 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 05DB01FB; Mon, 14 Jun 2021 07:57:33 -0700 (PDT) Received: from 010265703453.arm.com (unknown [10.57.9.136]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id E17EF3F70D; Mon, 14 Jun 2021 07:57:31 -0700 (PDT) From: Robin Murphy To: joro@8bytes.org Cc: will@kernel.org, john.garry@huawei.com, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, baolu.lu@linux.intel.com Subject: [PATCH] iommu: Update "iommu.strict" documentation Date: Mon, 14 Jun 2021 15:57:26 +0100 Message-Id: <2c8c06e1b449d6b060c5bf9ad3b403cd142f405d.1623682646.git.robin.murphy@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Consolidating the flush queue logic also meant that the "iommu.strict" option started taking effect on x86 as well. Make sure we document that. Fixes: a250c23f15c2 ("iommu: remove DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE") Signed-off-by: Robin Murphy --- Documentation/admin-guide/kernel-parameters.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index cb89dbdedc46..20a32de990ed 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -1987,7 +1987,7 @@ forcing Dual Address Cycle for PCI cards supporting greater than 32-bit addressing. - iommu.strict= [ARM64] Configure TLB invalidation behaviour + iommu.strict= [ARM64, X86] Configure TLB invalidation behaviour Format: { "0" | "1" } 0 - Lazy mode. Request that DMA unmap operations use deferred @@ -1998,6 +1998,10 @@ 1 - Strict mode (default). DMA unmap operations invalidate IOMMU hardware TLBs synchronously. + Note: on x86, the default behaviour depends on the + equivalent driver-specific parameters, but a strict + mode explicitly specified by either method takes + precedence. iommu.passthrough= [ARM64, X86] Configure DMA to bypass the IOMMU by default. -- 2.25.1