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Mon, 14 Jun 2021 17:48:36 +0000 From: Krishna Reddy To: Sai Prakash Ranjan , Robin Murphy CC: "linux-arm-msm@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "iommu@lists.linux-foundation.org" , Will Deacon , "linux-arm-kernel@lists.infradead.org" , Thierry Reding Subject: RE: [PATCH] iommu/io-pgtable-arm: Optimize partial walk flush for large scatter-gather list Thread-Topic: [PATCH] iommu/io-pgtable-arm: Optimize partial walk flush for large scatter-gather list Thread-Index: AQHXXT84btg0466hEE2rkvq94oyuZasMBHAAgACy+QCAAD6WAIAAB6mAgAAg2ACAAAWcgIAAPESAgACQdxCAAA05AIABAqfQgACvFQCABA+AcA== Date: Mon, 14 Jun 2021 17:48:36 +0000 Message-ID: References: <20210609145315.25750-1-saiprakash.ranjan@codeaurora.org> <35bfd245-45e2-8083-b620-330d6dbd7bd7@arm.com> <12067ffb8243b220cf03e83aaac3e823@codeaurora.org> <266f190e-99ae-9175-cf13-7a77730af389@arm.com> <61c69d23-324a-85d7-2458-dfff8df9280b@arm.com> <07001b4ed6c0a491eacce6e4dc13ab5e@codeaurora.org> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: codeaurora.org; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BY5PR12MB3764.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: d243624d-1bd2-47de-3da1-08d92f5ca2ee X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Jun 2021 17:48:36.5055 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: SeXKMeWw3I0Cszd3zBKVhSjtAvsjiYvd0C/nrRcsS9VrQjeEEcdRz02iJb5198l9NdxjvsEXeX2e5Dy+oYVL2g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB3077 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > Right but we won't know until we profile the specific usecases or try the= m in > generic workload to see if they affect the performance. Sure, over invali= dation is > a concern where multiple buffers can be mapped to same context and the ca= che > is not usable at the time for lookup and such but we don't do it for smal= l buffers > and only for large buffers which means thousands of TLB entry mappings in > which case TLBIASID is preferred (note: I mentioned the HW team > recommendation to use it for anything greater than 128 TLB entries) in my > earlier reply. And also note that we do this only for partial walk flush,= we are not > arbitrarily changing all the TLBIs to ASID based. Most of the heavy bw use cases does involve processing larger buffers. When the physical memory is allocated dis-contiguously at page_size (let's = use 4KB here) granularity, each aligned 2MB chunks IOVA unmap would involve performing a = TLBIASID as 2MB is not a leaf. Essentially, It happens all the time during large buf= fer unmaps and potentially impact active traffic on other large buffers. Depending on how = much latency HW engines can absorb, the overflow/underflow issues for ISO engine= s can be sporadic and vendor specific.=20 Performing TLBIASID as default for all SoCs is not a safe operation. > I am no camera expert but from what the camera team mentioned is that the= re > is a thread which frees memory(large unused memory buffers) periodically = which > ends up taking around 100+ms and causing some camera test failures with > frame drops. Parallel efforts are already being made to optimize this usa= ge of > thread but as I mentioned previously, this is *not a camera specific*, le= ts say > someone else invokes such large unmaps, it's going to face the same issue= . From the above, It doesn't look like the root cause of frame drops is fully= understood. Why is 100+ms delay causing camera frame drop? Is the same thread submitti= ng the buffers to camera after unmap is complete? If not, how is the unmap latency causing= issue here? =20 > > If unmap is queued and performed on a back ground thread, would it > > resolve the frame drops? >=20 > Not sure I understand what you mean by queuing on background thread but w= ith > that or not, we still do the same number of TLBIs and hop through > iommu->io-pgtable->arm-smmu to perform the the unmap, so how will that > help? I mean adding the unmap requests into a queue and processing them from a di= fferent thread. It is not to reduce the TLBIs. But, not to block subsequent buffer allocati= on, IOVA map requests, if they are being requested from same thread that is performing unmap. If unmap is = already performed from a different thread, then the issue still need to be root caused to understa= nd it fully. Check for any serialization issues.=20 -KR