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Tue, 15 Jun 2021 03:28:10 -0700 Envelope-to: git@xilinx.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, robh+dt@kernel.org, bgolaszewski@baylibre.com, linus.walleij@linaro.org Received: from [172.30.17.109] (port=33904) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1lt6Ii-0007uT-TC; Tue, 15 Jun 2021 03:28:09 -0700 Subject: Re: [PATCH 1/2] dt-bindings: gpio: Add binding documentation for modepin To: Piyush Mehta , , , , , , CC: , , , References: <20210615080553.2021061-1-piyush.mehta@xilinx.com> <20210615080553.2021061-2-piyush.mehta@xilinx.com> From: Michal Simek Message-ID: Date: Tue, 15 Jun 2021 12:28:06 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210615080553.2021061-2-piyush.mehta@xilinx.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7c30edf3-8e70-48bb-36d6-08d92fe84685 X-MS-TrafficTypeDiagnostic: BYAPR02MB5800: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:3968; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jun 2021 10:28:11.0889 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7c30edf3-8e70-48bb-36d6-08d92fe84685 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0044.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR02MB5800 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 6/15/21 10:05 AM, Piyush Mehta wrote: > Add DT binding document for modepin GPIO controller. > > Signed-off-by: Piyush Mehta > State: pending note: this shouldn't be the part of commit message. But please wait when dt guys review this file and then send v2. M > --- > .../bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml | 41 ++++++++++++++++++++++ > 1 file changed, 41 insertions(+) > create mode 100644 Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml > > diff --git a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml > new file mode 100644 > index 0000000..39d78f8 > --- /dev/null > +++ b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml > @@ -0,0 +1,41 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: ZynqMP Mode Pin GPIO controller > + > +description: > + PS_MODE is 4-bits boot mode pins sampled on POR deassertion. Mode Pin > + GPIO controller with configurable from numbers of pins (from 0 to 3 per > + PS_MODE). Every pin can be configured as input/output. > + > +maintainers: > + - Piyush Mehta > + > +properties: > + compatible: > + const: xlnx,zynqmp-gpio-modepin > + > + gpio-controller: true > + > + "#gpio-cells": > + const: 2 > + > +required: > + - compatible > + - gpio-controller > + - "#gpio-cells" > + > +additionalProperties: false > + > +examples: > + - | > + modepin_gpio: gpio { > + compatible = "xlnx,zynqmp-gpio-modepin"; > + gpio-controller; > + #gpio-cells = <2>; > + }; > + > +... >