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Tue, 15 Jun 2021 11:34:17 +0000 Subject: Re: [PATCH v9 2/3] dmaengine: ptdma: register PTDMA controller as a DMA resource To: Vinod Koul , Sanjay R Mehta Cc: gregkh@linuxfoundation.org, dan.j.williams@intel.com, Thomas.Lendacky@amd.com, Shyam-sundar.S-k@amd.com, Nehal-bakulchandra.Shah@amd.com, robh@kernel.org, mchehab+samsung@kernel.org, davem@davemloft.net, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org References: <1622654551-9204-1-git-send-email-Sanju.Mehta@amd.com> <1622654551-9204-3-git-send-email-Sanju.Mehta@amd.com> From: Sanjay R Mehta Message-ID: <311d14a1-39f4-1aad-bce0-a64fee52d13b@amd.com> Date: Tue, 15 Jun 2021 17:04:04 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [165.204.158.249] X-ClientProxiedBy: SGXP274CA0008.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:b8::20) To DM4PR12MB5103.namprd12.prod.outlook.com (2603:10b6:5:392::13) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from [10.252.253.16] (165.204.158.249) by SGXP274CA0008.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:b8::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4219.20 via Frontend Transport; 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>> + >> + desc = kmem_cache_zalloc(chan->pt->dma_desc_cache, GFP_NOWAIT); >> + if (!desc) >> + return NULL; >> + >> + vchan_tx_prep(&chan->vc, &desc->vd, flags); >> + >> + desc->pt = chan->pt; >> + desc->issued_to_hw = 0; >> + INIT_LIST_HEAD(&desc->cmdlist); > > why do you need your own list, the lists in vc should suffice? > Do you think this should be a major blocker for pulling this series in 5.14? Would you be okay to accept this change in the subsequent driver updates? >> +static int pt_resume(struct dma_chan *dma_chan) >> +{ >> + struct pt_dma_chan *chan = to_pt_chan(dma_chan); >> + struct pt_dma_desc *desc = NULL; >> + unsigned long flags; >> + >> + spin_lock_irqsave(&chan->vc.lock, flags); >> + pt_start_queue(&chan->pt->cmd_q); >> + desc = __pt_next_dma_desc(chan); >> + spin_unlock_irqrestore(&chan->vc.lock, flags); >> + >> + /* If there was something active, re-start */ >> + if (desc) >> + pt_cmd_callback(desc, 0); > > this doesn't sound correct. In pause yoy stop the queue, so start of the > queue should be done here... Why grab a descriptor? > >> +static int pt_terminate_all(struct dma_chan *dma_chan) >> +{ >> + struct pt_dma_chan *chan = to_pt_chan(dma_chan); >> + >> + vchan_free_chan_resources(&chan->vc); > > what about the descriptors, are you not going to clear the lists and > free them.. > >> +int pt_dmaengine_register(struct pt_device *pt) >> +{ >> + struct pt_dma_chan *chan; >> + struct dma_device *dma_dev = &pt->dma_dev; >> + char *cmd_cache_name; >> + char *desc_cache_name; >> + int ret; >> + >> + pt->pt_dma_chan = devm_kzalloc(pt->dev, sizeof(*pt->pt_dma_chan), >> + GFP_KERNEL); >> + if (!pt->pt_dma_chan) >> + return -ENOMEM; >> + >> + cmd_cache_name = devm_kasprintf(pt->dev, GFP_KERNEL, >> + "%s-dmaengine-cmd-cache", >> + pt->name); >> + if (!cmd_cache_name) >> + return -ENOMEM; >> + >> + pt->dma_cmd_cache = kmem_cache_create(cmd_cache_name, >> + sizeof(struct pt_dma_cmd), >> + sizeof(void *), >> + SLAB_HWCACHE_ALIGN, NULL); >> + if (!pt->dma_cmd_cache) >> + return -ENOMEM; >> + >> + desc_cache_name = devm_kasprintf(pt->dev, GFP_KERNEL, >> + "%s-dmaengine-desc-cache", >> + pt->name); >> + if (!desc_cache_name) { >> + ret = -ENOMEM; >> + goto err_cache; >> + } >> + >> + pt->dma_desc_cache = kmem_cache_create(desc_cache_name, >> + sizeof(struct pt_dma_desc), >> + sizeof(void *), > > sizeof void ptr? > >> + SLAB_HWCACHE_ALIGN, NULL); >> + if (!pt->dma_desc_cache) { >> + ret = -ENOMEM; >> + goto err_cache; >> + } >> + >> + dma_dev->dev = pt->dev; >> + dma_dev->src_addr_widths = DMA_SLAVE_BUSWIDTH_64_BYTES; >> + dma_dev->dst_addr_widths = DMA_SLAVE_BUSWIDTH_64_BYTES; >> + dma_dev->directions = DMA_MEM_TO_MEM; >> + dma_dev->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR; >> + dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask); >> + dma_cap_set(DMA_INTERRUPT, dma_dev->cap_mask); >> + dma_cap_set(DMA_PRIVATE, dma_dev->cap_mask); > > Why DMA_PRIVATE ? this is a dma mempcy controller ... This DMA controller is intended to be used with AMD Non-Transparent Bridge devices and not for general purpose peripheral DMA. Hence marking it as DMA_PRIVATE. - Sanjay