Received: by 2002:a05:6a10:206:0:0:0:0 with SMTP id 6csp3861804pxj; Tue, 15 Jun 2021 10:11:42 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzX+b9K18JIoVlxMRSFHBi/J0lLb5lDFCsmoJSIzj92VFIqaTI5Am6UmCBnZoRGSe9Ld3uP X-Received: by 2002:a05:6402:cb1:: with SMTP id cn17mr671383edb.42.1623777102743; Tue, 15 Jun 2021 10:11:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1623777102; cv=none; d=google.com; s=arc-20160816; b=IReGWDuTeDXrexYT6TVrObnr2stcPtBX60yVH51KwIOpVQf6JTuj9ucvwUJInZMoUW hU283SBkcirfex9lp/dyrLxmA+wJhtOsBXZO3Bqwlq6H00eli8KjR0q+d/FsbmD/CXO8 XiTCdTDHokemhLmfnZTd6NQulstj7iB+qAvRCz906uSIHZ/30Utb/sO3WZ1oH/4pypLl BWQ7U9TBXNHg1rC28swUIJrstMl+6+6vhlKVxGIZ2lhVbDrGggkCzZGBUPEq0sYUmk7X kocfEv/MXAET5z8k3RstUsQYLB0JU9AJ++UZwOH9GG8s4sN8BcwrIqy8MCCzSywFz0D2 dJWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=Fs8XY3CuIbReqXGQIbUihHuuFnBEF23NiwdMPxjEqsI=; b=VHMd8fcKwRmuBg/Of0Cvfv3xInz63Wky3kNQZ6kpGQ8qrDpfO9qJcgpgpKiVp2wVQ8 dVmRu+1K1n3Mz63Ng+7ljXaQbnyQ9k+s4Y4TTjrAPR5C5VRjUiMQEuXpSVSx4f9QzNva G1uzwGPPQ1Ccl0KLslytdG5FDTE2JsXQUIuYx8t6QfKm5ZnEU9hHuPAzHz9SPYKvNK4J cYwlJkOCyfDDnsixq29ayZFEfw7tzIayXv09QOscunZPNhpSZE5dLjwWVLbpuRqd3nG2 7rKkdjwTG884VCvC0WzAwTZA/XO/PtCuCnyVU6J8r4m97RU+OmXZBNMB2qAssFkCgJnZ 1GYw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@quicinc.com header.s=qcdkim header.b=RJ2tST1Q; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id d4si15449593ejo.252.2021.06.15.10.11.14; Tue, 15 Jun 2021 10:11:42 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=fail header.i=@quicinc.com header.s=qcdkim header.b=RJ2tST1Q; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231576AbhFORLX (ORCPT + 99 others); Tue, 15 Jun 2021 13:11:23 -0400 Received: from alexa-out-sd-02.qualcomm.com ([199.106.114.39]:34909 "EHLO alexa-out-sd-02.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231229AbhFORK6 (ORCPT ); Tue, 15 Jun 2021 13:10:58 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1623776933; x=1655312933; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=RkUxbPOsV+XN7vIXyWNniRgdCryIUPWS7ilq0vkeuZQ=; b=RJ2tST1Q+cDvrsDM6YN2gRfBUU++ZOLkkTU8gOSDYci6BOzV3QrMsoaM wU0jyS/LtZkQzDekdqAb3mRV6vLEFiXHEHRKmU4drzRxcdJuEe1LiAVEN PJfEEv8b//MTeEWwVwa6122UjzoEtmBz+GwGVwCJOlomanE8YUkBQnzc+ A=; Received: from unknown (HELO ironmsg01-sd.qualcomm.com) ([10.53.140.141]) by alexa-out-sd-02.qualcomm.com with ESMTP; 15 Jun 2021 10:08:53 -0700 X-QCInternal: smtphost Received: from nasanexm03e.na.qualcomm.com ([10.85.0.48]) by ironmsg01-sd.qualcomm.com with ESMTP/TLS/AES256-SHA; 15 Jun 2021 10:08:53 -0700 Received: from th-lint-040.qualcomm.com (10.80.80.8) by nasanexm03e.na.qualcomm.com (10.85.0.48) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 15 Jun 2021 10:08:53 -0700 From: Georgi Djakov To: , CC: , , , , , , , Subject: [PATCH v6 11/15] iommu/io-pgtable-arm: Implement arm_lpae_map_pages() Date: Tue, 15 Jun 2021 10:08:29 -0700 Message-ID: <1623776913-390160-12-git-send-email-quic_c_gdjako@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1623776913-390160-1-git-send-email-quic_c_gdjako@quicinc.com> References: <1623776913-390160-1-git-send-email-quic_c_gdjako@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanexm03e.na.qualcomm.com (10.85.0.48) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: "Isaac J. Manjarres" Implement the map_pages() callback for the ARM LPAE io-pgtable format. Signed-off-by: Isaac J. Manjarres Signed-off-by: Georgi Djakov --- drivers/iommu/io-pgtable-arm.c | 41 +++++++++++++++++++++++++++++++---------- 1 file changed, 31 insertions(+), 10 deletions(-) diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c index 1b690911995a..6a6af9b0678e 100644 --- a/drivers/iommu/io-pgtable-arm.c +++ b/drivers/iommu/io-pgtable-arm.c @@ -344,20 +344,30 @@ static arm_lpae_iopte arm_lpae_install_table(arm_lpae_iopte *table, } static int __arm_lpae_map(struct arm_lpae_io_pgtable *data, unsigned long iova, - phys_addr_t paddr, size_t size, arm_lpae_iopte prot, - int lvl, arm_lpae_iopte *ptep, gfp_t gfp) + phys_addr_t paddr, size_t size, size_t pgcount, + arm_lpae_iopte prot, int lvl, arm_lpae_iopte *ptep, + gfp_t gfp, size_t *mapped) { arm_lpae_iopte *cptep, pte; size_t block_size = ARM_LPAE_BLOCK_SIZE(lvl, data); size_t tblsz = ARM_LPAE_GRANULE(data); struct io_pgtable_cfg *cfg = &data->iop.cfg; + int ret = 0, num_entries, max_entries, map_idx_start; /* Find our entry at the current level */ - ptep += ARM_LPAE_LVL_IDX(iova, lvl, data); + map_idx_start = ARM_LPAE_LVL_IDX(iova, lvl, data); + ptep += map_idx_start; /* If we can install a leaf entry at this level, then do so */ - if (size == block_size) - return arm_lpae_init_pte(data, iova, paddr, prot, lvl, 1, ptep); + if (size == block_size) { + max_entries = ARM_LPAE_PTES_PER_TABLE(data) - map_idx_start; + num_entries = min_t(int, pgcount, max_entries); + ret = arm_lpae_init_pte(data, iova, paddr, prot, lvl, num_entries, ptep); + if (!ret && mapped) + *mapped += num_entries * size; + + return ret; + } /* We can't allocate tables at the final level */ if (WARN_ON(lvl >= ARM_LPAE_MAX_LEVELS - 1)) @@ -386,7 +396,8 @@ static int __arm_lpae_map(struct arm_lpae_io_pgtable *data, unsigned long iova, } /* Rinse, repeat */ - return __arm_lpae_map(data, iova, paddr, size, prot, lvl + 1, cptep, gfp); + return __arm_lpae_map(data, iova, paddr, size, pgcount, prot, lvl + 1, + cptep, gfp, mapped); } static arm_lpae_iopte arm_lpae_prot_to_pte(struct arm_lpae_io_pgtable *data, @@ -453,8 +464,9 @@ static arm_lpae_iopte arm_lpae_prot_to_pte(struct arm_lpae_io_pgtable *data, return pte; } -static int arm_lpae_map(struct io_pgtable_ops *ops, unsigned long iova, - phys_addr_t paddr, size_t size, int iommu_prot, gfp_t gfp) +static int arm_lpae_map_pages(struct io_pgtable_ops *ops, unsigned long iova, + phys_addr_t paddr, size_t pgsize, size_t pgcount, + int iommu_prot, gfp_t gfp, size_t *mapped) { struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops); struct io_pgtable_cfg *cfg = &data->iop.cfg; @@ -463,7 +475,7 @@ static int arm_lpae_map(struct io_pgtable_ops *ops, unsigned long iova, arm_lpae_iopte prot; long iaext = (s64)iova >> cfg->ias; - if (WARN_ON(!size || (size & cfg->pgsize_bitmap) != size)) + if (WARN_ON(!pgsize || (pgsize & cfg->pgsize_bitmap) != pgsize)) return -EINVAL; if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1) @@ -476,7 +488,8 @@ static int arm_lpae_map(struct io_pgtable_ops *ops, unsigned long iova, return 0; prot = arm_lpae_prot_to_pte(data, iommu_prot); - ret = __arm_lpae_map(data, iova, paddr, size, prot, lvl, ptep, gfp); + ret = __arm_lpae_map(data, iova, paddr, pgsize, pgcount, prot, lvl, + ptep, gfp, mapped); /* * Synchronise all PTE updates for the new mapping before there's * a chance for anything to kick off a table walk for the new iova. @@ -486,6 +499,13 @@ static int arm_lpae_map(struct io_pgtable_ops *ops, unsigned long iova, return ret; } +static int arm_lpae_map(struct io_pgtable_ops *ops, unsigned long iova, + phys_addr_t paddr, size_t size, int iommu_prot, gfp_t gfp) +{ + return arm_lpae_map_pages(ops, iova, paddr, size, 1, iommu_prot, gfp, + NULL); +} + static void __arm_lpae_free_pgtable(struct arm_lpae_io_pgtable *data, int lvl, arm_lpae_iopte *ptep) { @@ -782,6 +802,7 @@ arm_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg) data->iop.ops = (struct io_pgtable_ops) { .map = arm_lpae_map, + .map_pages = arm_lpae_map_pages, .unmap = arm_lpae_unmap, .unmap_pages = arm_lpae_unmap_pages, .iova_to_phys = arm_lpae_iova_to_phys,