Received: by 2002:a05:6a10:206:0:0:0:0 with SMTP id 6csp3884142pxj; Tue, 15 Jun 2021 10:39:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxKFFuXQJ+kXgieXLliTTqr6zah6E0y6Yvtw7CLfWktmmtnEm6yy6uERqepuYJDYIAOrN4o X-Received: by 2002:a17:906:e10d:: with SMTP id gj13mr794838ejb.150.1623778742698; Tue, 15 Jun 2021 10:39:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1623778742; cv=none; d=google.com; s=arc-20160816; b=cvjnjCGzmJ5WcuCOr80LHu5T2StXFPGsG+lzEMsSK7g3xkhRCW6Tdk2DF2ABMEaBgY 1GA82qRHwZAIQiF9fDCW7KPSXQXo2WuXDQa/WI7WHA6YiTdyu2FB3f1SaH1Grvupq907 l5lObHzTvlaIUfO88Gdjq0kIgLf2I+IebEVAvcEak6BaO8JGzS1JSzHNXq+Qig0GcK3z nxVSx7JRw1wOkqmkxs1evLmd+tXdUZCETmGkNFz8uJnd7e9rsT3eD8SatTbo1+E2fzv4 7N0EbNP0ga3P31uodI6YaK3XB0i55G/7e0w8V0ypkMhO9S1ofj5EHAW74MpQvPqdOMDK tzAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from; bh=V+/ymf6WXVxJnuDqwg8RelVdDH5t+6wURC8f4Wgp3SU=; b=DqZox90ZK3OJCkmdLcyMlRGcy7cwtmA298nBZ6tVvygCqSt5fwEOZ1xNsYGOQdPOQz ZD7+NjnO2KLUiCNfP4XIIYLC2T5oCQQ3CWIauqLhzasrHDOhbwYbCd+HinLfRMFEXCCX ohuvLw6y5XP/f6q1om2repA49udXB/rXWj8RGBolsyz/3zKaXEaARpC8uiV/vdBXhjy0 J/jkc+7MKDKrl+c6n0PTpoqtVcp2hB+I3gIOGwDe+c8NOGtYXI3lfrIBxiPokzXw0hAc +IydleSjjEvZPzyan5E5CTXAo64q5BCTECBaxOMnQjFQriLoZzshLJX0GAoRPTEsGyEj 0N3g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id jg35si2252099ejc.323.2021.06.15.10.38.39; Tue, 15 Jun 2021 10:39:02 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231213AbhFORgZ (ORCPT + 99 others); Tue, 15 Jun 2021 13:36:25 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:34925 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231341AbhFORfA (ORCPT ); Tue, 15 Jun 2021 13:35:00 -0400 X-UUID: 3fcc64b316c44cc6971b1d2739854cb4-20210616 X-UUID: 3fcc64b316c44cc6971b1d2739854cb4-20210616 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 202066784; Wed, 16 Jun 2021 01:32:49 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Jun 2021 01:32:42 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 16 Jun 2021 01:32:42 +0800 From: Tinghan Shen To: , CC: , , , , , , , , Henry Chen Subject: [PATCH 03/27] arm64: dts: mt8195: add pwrap node Date: Wed, 16 Jun 2021 01:32:10 +0800 Message-ID: <20210615173233.26682-4-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.15.GIT In-Reply-To: <20210615173233.26682-1-tinghan.shen@mediatek.com> References: <20210615173233.26682-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Henry Chen Add pwrap node to SOC MT8195. Signed-off-by: Henry Chen --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 640f09100bb7..bbb1e008e522 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -322,6 +322,18 @@ clocks = <&clk26m>; }; + pwrap: pwrap@10024000 { + compatible = "mediatek,mt8195-pwrap", "syscon"; + reg = <0 0x10024000 0 0x1000>; + reg-names = "pwrap"; + interrupts = ; + clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, + <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; + clock-names = "spi", "wrap"; + assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC_D10>; + }; + uart0: serial@11001100 { compatible = "mediatek,mt8195-uart", "mediatek,mt6577-uart"; reg = <0 0x11001100 0 0x100>; -- 2.18.0