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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id e23sm209800otk.67.2021.06.15.19.41.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Jun 2021 19:41:09 -0700 (PDT) Date: Tue, 15 Jun 2021 21:41:07 -0500 From: Bjorn Andersson To: Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, martin.botka@somainline.org, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, jamipkettunen@somainline.org, Andy Gross , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/6] arm64: dts: qcom: sm8250: Commonize PCIe pins Message-ID: References: <20210616005843.79579-1-konrad.dybcio@somainline.org> <20210616005843.79579-2-konrad.dybcio@somainline.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210616005843.79579-2-konrad.dybcio@somainline.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue 15 Jun 19:58 CDT 2021, Konrad Dybcio wrote: [..] > diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi [..] > @@ -3490,6 +3508,89 @@ data { > bias-pull-up; > }; > }; > + > + pcie0_default_state: pcie0-default { I thought I answered the other way around (that it should be in the board file), that said I don't think these are moving much, so I'm not against keeping them here. > + pcie0_perst_default: perst { > + pins = "gpio79"; > + function = "gpio"; > + drive-strength = <2>; > + bias-pull-down; > + }; > + > + clkreq { > + pins = "gpio80"; > + function = "pci_e0"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + wake { > + pins = "gpio81"; > + function = "gpio"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + }; [..] > + > + mdm2ap_default: mdm2ap-default { These however are presumably only present on devices with SDX55, so please move these two to your board file. Thanks, Bjorn