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From:   Bin Meng <bmeng.cn@gmail.com>
To:     Palmer Dabbelt <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Atish Patra <atish.patra@wdc.com>,
        linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
Cc:     Bin Meng <bin.meng@windriver.com>
Subject: [PATCH] riscv: dts: microchip: Define hart clocks
Date:   Wed, 16 Jun 2021 14:27:39 +0800
Message-Id: <20210616062739.398790-1-bmeng.cn@gmail.com>
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From: Bin Meng <bin.meng@windriver.com>

Declare that each hart in the DT is clocked by <&clkcfg 0>.

Signed-off-by: Bin Meng <bin.meng@windriver.com>

---
Similar to https://patchwork.kernel.org/project/linux-riscv/patch/1592308864-30205-3-git-send-email-yash.shah@sifive.com/,
this adds the same <clock> property to PolarFire SoC CPU nodes so that we can
calculate the running frequency of the hart.

 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index a00d9dc560d3..0659068b62f7 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -24,6 +24,7 @@ cpu@0 {
 			i-cache-size = <16384>;
 			reg = <0>;
 			riscv,isa = "rv64imac";
+			clocks = <&clkcfg 0>;
 			status = "disabled";
 
 			cpu0_intc: interrupt-controller {
@@ -50,6 +51,7 @@ cpu@1 {
 			reg = <1>;
 			riscv,isa = "rv64imafdc";
 			tlb-split;
+			clocks = <&clkcfg 0>;
 			status = "okay";
 
 			cpu1_intc: interrupt-controller {
@@ -76,6 +78,7 @@ cpu@2 {
 			reg = <2>;
 			riscv,isa = "rv64imafdc";
 			tlb-split;
+			clocks = <&clkcfg 0>;
 			status = "okay";
 
 			cpu2_intc: interrupt-controller {
@@ -102,6 +105,7 @@ cpu@3 {
 			reg = <3>;
 			riscv,isa = "rv64imafdc";
 			tlb-split;
+			clocks = <&clkcfg 0>;
 			status = "okay";
 
 			cpu3_intc: interrupt-controller {
@@ -128,6 +132,7 @@ cpu@4 {
 			reg = <4>;
 			riscv,isa = "rv64imafdc";
 			tlb-split;
+			clocks = <&clkcfg 0>;
 			status = "okay";
 			cpu4_intc: interrupt-controller {
 				#interrupt-cells = <1>;
-- 
2.25.1