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Subject: Re: [PATCH 25/31] arm64: zynqmp: Wire qspi on multiple boards
To:     Michal Simek <michal.simek@xilinx.com>,
        linux-kernel@vger.kernel.org, monstr@monstr.eu, git@xilinx.com,
        Viresh Kumar <viresh.kumar@linaro.org>
Cc:     Krzysztof Kozlowski <krzk@kernel.org>,
        Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
        Rob Herring <robh+dt@kernel.org>, devicetree@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org
References: <cover.1623239033.git.michal.simek@xilinx.com>
 <80671218c97ad2188df476cf1b49bcf6f64785df.1623239033.git.michal.simek@xilinx.com>
 <71b6423c-ab14-424f-0018-fafece13150a@windriver.com>
 <d8d3f8e9-d59d-be12-05dd-5fa9b64cfcbe@xilinx.com>
From:   "quanyang.wang" <quanyang.wang@windriver.com>
Message-ID: <fcba2eee-4330-ec39-6880-70af201944a1@windriver.com>
Date:   Wed, 16 Jun 2021 19:15:12 +0800
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Hi Michal,

On 6/16/21 6:52 PM, Michal Simek wrote:
> Hi Quanyang,
> 
> On 6/10/21 6:08 AM, quanyang.wang wrote:
>> Hi Michal,
>>
>> On 6/9/21 7:45 PM, Michal Simek wrote:
>>> Couple of boards have qspi on the board that's why enable controller and
>>> describe them.
>>>
>>> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
>>> ---
>>>
>>>    .../arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 16 +++++++++++++++-
>>>    .../arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 16 +++++++++++++++-
>>>    .../boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts  | 14 ++++++++++++++
>>>    .../boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts  | 14 ++++++++++++++
>>>    .../arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 15 +++++++++++++++
>>>    .../arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 14 ++++++++++++++
>>>    .../arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts |  4 ++++
>>>    .../arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 15 +++++++++++++++
>>>    .../arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 15 +++++++++++++++
>>>    9 files changed, 121 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
>>> b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
>>> index 2e05fa416955..f1598527e5ec 100644
>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
>>> @@ -2,7 +2,7 @@
>>>    /*
>>>     * dts file for Xilinx ZynqMP ZC1232
>>>     *
>>> - * (C) Copyright 2017 - 2019, Xilinx, Inc.
>>> + * (C) Copyright 2017 - 2021, Xilinx, Inc.
>>>     *
>>>     * Michal Simek <michal.simek@xilinx.com>
>>>     */
>>> @@ -19,6 +19,7 @@ / {
>>>        aliases {
>>>            serial0 = &uart0;
>>>            serial1 = &dcc;
>>> +        spi0 = &qspi;
>>>        };
>>>          chosen {
>>> @@ -36,6 +37,19 @@ &dcc {
>>>        status = "okay";
>>>    };
>>>    +&qspi {
>>> +    status = "okay";
>>> +    flash@0 {
>>> +        compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
>>> +        #address-cells = <1>;
>>> +        #size-cells = <1>;
>>> +        reg = <0x0>;
>>> +        spi-tx-bus-width = <1>;
>>> +        spi-rx-bus-width = <4>;
>>> +        spi-max-frequency = <108000000>; /* Based on DC1 spec */
>>> +    };
>>> +};
>>> +
>>>    &sata {
>>>        status = "okay";
>>>        /* SATA OOB timing settings */
>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
>>> b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
>>> index 3d0aaa02f184..04efa1683eaa 100644
>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
>>> @@ -2,7 +2,7 @@
>>>    /*
>>>     * dts file for Xilinx ZynqMP ZC1254
>>>     *
>>> - * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>> + * (C) Copyright 2015 - 2021, Xilinx, Inc.
>>>     *
>>>     * Michal Simek <michal.simek@xilinx.com>
>>>     * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
>>> @@ -20,6 +20,7 @@ / {
>>>        aliases {
>>>            serial0 = &uart0;
>>>            serial1 = &dcc;
>>> +        spi0 = &qspi;
>>>        };
>>>          chosen {
>>> @@ -37,6 +38,19 @@ &dcc {
>>>        status = "okay";
>>>    };
>>>    +&qspi {
>>> +    status = "okay";
>>> +    flash@0 {
>>> +        compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
>>> +        #address-cells = <1>;
>>> +        #size-cells = <1>;
>>> +        reg = <0x0>;
>>> +        spi-tx-bus-width = <1>;
>>> +        spi-rx-bus-width = <4>; /* FIXME also DUAL configuration
>>> possible */
>>> +        spi-max-frequency = <108000000>; /* Based on DC1 spec */
>>> +    };
>>> +};
>>> +
>>>    &uart0 {
>>>        status = "okay";
>>>    };
>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
>>> b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
>>> index cd406947ec34..9f176307b62a 100644
>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
>>> @@ -26,6 +26,7 @@ aliases {
>>>            mmc1 = &sdhci1;
>>>            rtc0 = &rtc;
>>>            serial0 = &uart0;
>>> +        spi0 = &qspi;
>>>        };
>>>          chosen {
>>> @@ -339,6 +340,19 @@ conf {
>>>        };
>>>    };
>>>    +&qspi {
>>> +    status = "okay";
>>> +    flash@0 {
>>> +        compatible = "m25p80", "jedec,spi-nor"; /* Micron
>>> MT25QU512ABB8ESF */
>>> +        #address-cells = <1>;
>>> +        #size-cells = <1>;
>>> +        reg = <0x0>;
>>> +        spi-tx-bus-width = <1>;
>>> +        spi-rx-bus-width = <4>;
>>> +        spi-max-frequency = <108000000>; /* Based on DC1 spec */
>>> +    };
>>> +};
>>> +
>>>    &rtc {
>>>        status = "okay";
>>>    };
>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
>>> b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
>>> index 8046f0df0f35..05a2b79738af 100644
>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
>>> @@ -26,6 +26,7 @@ aliases {
>>>            rtc0 = &rtc;
>>>            serial0 = &uart0;
>>>            serial1 = &uart1;
>>> +        spi0 = &qspi;
>>>        };
>>>          chosen {
>>> @@ -161,6 +162,19 @@ &i2c1 {
>>>        status = "okay";
>>>    };
>>>    +&qspi {
>>> +    status = "okay";
>>> +    flash@0 {
>>> +        compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
>>> +        #address-cells = <1>;
>>> +        #size-cells = <1>;
>>> +        reg = <0x0>;
>>> +        spi-tx-bus-width = <1>;
>>> +        spi-rx-bus-width = <4>; /* also DUAL configuration possible */
>>> +        spi-max-frequency = <108000000>; /* Based on DC1 spec */
>>> +    };
>>> +};
>>> +
>>>    &rtc {
>>>        status = "okay";
>>>    };
>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>>> b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>>> index 3cbc51b4587d..becfc23a5610 100644
>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>>> @@ -30,6 +30,7 @@ aliases {
>>>            serial0 = &uart0;
>>>            serial1 = &uart1;
>>>            serial2 = &dcc;
>>> +        spi0 = &qspi;
>>>        };
>>>          chosen {
>>> @@ -934,6 +935,20 @@ &psgtr {
>>>        clock-names = "ref0", "ref1", "ref2", "ref3";
>>>    };
>>>    +&qspi {
>>> +    status = "okay";
>>> +    is-dual = <1>;
>>> +    flash@0 {
>>> +        compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
>> Maybe here should be "64MB" not "32MB".
>> There are 2 mt25qu512a flashes at zcu102 board, and each of them is
>> 64MB. Since "is-dual" mode is not enabled, so we can only observe 64MB
>> size from boot log:
>>
>> spi-nor spi0.0: found mt25qu512a, expected m25p80
>> spi-nor spi0.0: mt25qu512a (65536 Kbytes)
>>
>> And I only verify the flash size in zcu102 board and not sure if the
>> flash size comments are correct for other boards in this patch.
> 
> I have double checked revA and it really has 16MB+16MB configuration
> where only one is visible.
Sorry for the noise. I made a mistake checking it at the board zcu102 
Rev1.1 not RevA.

Best Regards,
Quanyang
> I will use only half of that listed size which is corresponding with
> single configuration and also remove is-dual from 102/106/111.
> 
> This change will be in v3 version because forget to include it in v2.
> 
> Thanks,
> Michal
>