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[23.128.96.18]) by mx.google.com with ESMTP id l15si2202621ejq.530.2021.06.16.05.20.25; Wed, 16 Jun 2021 05:20:47 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232555AbhFPLqo (ORCPT + 99 others); Wed, 16 Jun 2021 07:46:44 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:60885 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231476AbhFPLqn (ORCPT ); Wed, 16 Jun 2021 07:46:43 -0400 X-UUID: 2d61c4e5864e4005ba77c14063b488fe-20210616 X-UUID: 2d61c4e5864e4005ba77c14063b488fe-20210616 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1250267042; Wed, 16 Jun 2021 19:44:34 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Jun 2021 19:44:27 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 16 Jun 2021 19:44:26 +0800 From: Yong Wu To: Krzysztof Kozlowski , Rob Herring , Matthias Brugger CC: Krzysztof Kozlowski , Joerg Roedel , Will Deacon , Robin Murphy , Tomasz Figa , , , , , , , , , , , Subject: [PATCH 3/9] memory: mtk-smi: Use clk_bulk instead of the clk ops Date: Wed, 16 Jun 2021 19:43:40 +0800 Message-ID: <20210616114346.18812-4-yong.wu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210616114346.18812-1-yong.wu@mediatek.com> References: <20210616114346.18812-1-yong.wu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org smi have many clocks: apb/smi/gals. This patch use clk_bulk interface instead of the orginal one to simply the code. gals is optional clk(some larbs may don't have gals). use clk_bulk_optional instead. and then remove the has_gals flag. Also remove clk fail logs since bulk interface already output fail log. Signed-off-by: Yong Wu --- drivers/memory/mtk-smi.c | 124 +++++++++++---------------------------- 1 file changed, 34 insertions(+), 90 deletions(-) diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c index c5fb51f73b34..bcd2bf130655 100644 --- a/drivers/memory/mtk-smi.c +++ b/drivers/memory/mtk-smi.c @@ -60,9 +60,18 @@ enum mtk_smi_gen { MTK_SMI_GEN2 }; +#define MTK_SMI_CLK_NR_MAX 4 + +static const char * const mtk_smi_common_clocks[] = { + "apb", "smi", "gals0", "gals1", /* glas is optional */ +}; + +static const char * const mtk_smi_larb_clocks[] = { + "apb", "smi", "gals" +}; + struct mtk_smi_common_plat { enum mtk_smi_gen gen; - bool has_gals; u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */ }; @@ -70,13 +79,12 @@ struct mtk_smi_larb_gen { int port_in_larb[MTK_LARB_NR_MAX + 1]; void (*config_port)(struct device *dev); unsigned int larb_direct_to_common_mask; - bool has_gals; }; struct mtk_smi { struct device *dev; - struct clk *clk_apb, *clk_smi; - struct clk *clk_gals0, *clk_gals1; + unsigned int clk_num; + struct clk_bulk_data clks[MTK_SMI_CLK_NR_MAX]; struct clk *clk_async; /*only needed by mt2701*/ union { void __iomem *smi_ao_base; /* only for gen1 */ @@ -95,45 +103,6 @@ struct mtk_smi_larb { /* larb: local arbiter */ unsigned char *bank; }; -static int mtk_smi_clk_enable(const struct mtk_smi *smi) -{ - int ret; - - ret = clk_prepare_enable(smi->clk_apb); - if (ret) - return ret; - - ret = clk_prepare_enable(smi->clk_smi); - if (ret) - goto err_disable_apb; - - ret = clk_prepare_enable(smi->clk_gals0); - if (ret) - goto err_disable_smi; - - ret = clk_prepare_enable(smi->clk_gals1); - if (ret) - goto err_disable_gals0; - - return 0; - -err_disable_gals0: - clk_disable_unprepare(smi->clk_gals0); -err_disable_smi: - clk_disable_unprepare(smi->clk_smi); -err_disable_apb: - clk_disable_unprepare(smi->clk_apb); - return ret; -} - -static void mtk_smi_clk_disable(const struct mtk_smi *smi) -{ - clk_disable_unprepare(smi->clk_gals1); - clk_disable_unprepare(smi->clk_gals0); - clk_disable_unprepare(smi->clk_smi); - clk_disable_unprepare(smi->clk_apb); -} - int mtk_smi_larb_get(struct device *larbdev) { int ret = pm_runtime_resume_and_get(larbdev); @@ -270,7 +239,6 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = { }; static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = { - .has_gals = true, .config_port = mtk_smi_larb_config_port_gen2_general, .larb_direct_to_common_mask = BIT(2) | BIT(3) | BIT(7), /* IPU0 | IPU1 | CCU */ @@ -320,6 +288,7 @@ static int mtk_smi_larb_probe(struct platform_device *pdev) struct device_node *smi_node; struct platform_device *smi_pdev; struct device_link *link; + int i, ret; larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL); if (!larb) @@ -331,22 +300,14 @@ static int mtk_smi_larb_probe(struct platform_device *pdev) if (IS_ERR(larb->base)) return PTR_ERR(larb->base); - larb->smi.clk_apb = devm_clk_get(dev, "apb"); - if (IS_ERR(larb->smi.clk_apb)) - return PTR_ERR(larb->smi.clk_apb); - - larb->smi.clk_smi = devm_clk_get(dev, "smi"); - if (IS_ERR(larb->smi.clk_smi)) - return PTR_ERR(larb->smi.clk_smi); - - if (larb->larb_gen->has_gals) { - /* The larbs may still haven't gals even if the SoC support.*/ - larb->smi.clk_gals0 = devm_clk_get(dev, "gals"); - if (PTR_ERR(larb->smi.clk_gals0) == -ENOENT) - larb->smi.clk_gals0 = NULL; - else if (IS_ERR(larb->smi.clk_gals0)) - return PTR_ERR(larb->smi.clk_gals0); - } + larb->smi.clk_num = ARRAY_SIZE(mtk_smi_larb_clocks); + for (i = 0; i < larb->smi.clk_num; i++) + larb->smi.clks[i].id = mtk_smi_larb_clocks[i]; + + ret = devm_clk_bulk_get_optional(dev, larb->smi.clk_num, larb->smi.clks); + if (ret) + return ret; + larb->smi.dev = dev; smi_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0); @@ -391,11 +352,9 @@ static int __maybe_unused mtk_smi_larb_resume(struct device *dev) const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen; int ret; - ret = mtk_smi_clk_enable(&larb->smi); - if (ret < 0) { - dev_err(dev, "Failed to enable clock(%d).\n", ret); + ret = clk_bulk_prepare_enable(larb->smi.clk_num, larb->smi.clks); + if (ret < 0) return ret; - } /* Configure the basic setting for this larb */ larb_gen->config_port(dev); @@ -407,7 +366,7 @@ static int __maybe_unused mtk_smi_larb_suspend(struct device *dev) { struct mtk_smi_larb *larb = dev_get_drvdata(dev); - mtk_smi_clk_disable(&larb->smi); + clk_bulk_disable_unprepare(larb->smi.clk_num, larb->smi.clks); return 0; } @@ -437,21 +396,18 @@ static const struct mtk_smi_common_plat mtk_smi_common_gen2 = { static const struct mtk_smi_common_plat mtk_smi_common_mt6779 = { .gen = MTK_SMI_GEN2, - .has_gals = true, .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(4) | F_MMU1_LARB(5) | F_MMU1_LARB(6) | F_MMU1_LARB(7), }; static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = { .gen = MTK_SMI_GEN2, - .has_gals = true, .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) | F_MMU1_LARB(7), }; static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = { .gen = MTK_SMI_GEN2, - .has_gals = true, .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) | F_MMU1_LARB(6), }; @@ -493,7 +449,7 @@ static int mtk_smi_common_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct mtk_smi *common; struct resource *res; - int ret; + int i, ret; common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL); if (!common) @@ -501,23 +457,13 @@ static int mtk_smi_common_probe(struct platform_device *pdev) common->dev = dev; common->plat = of_device_get_match_data(dev); - common->clk_apb = devm_clk_get(dev, "apb"); - if (IS_ERR(common->clk_apb)) - return PTR_ERR(common->clk_apb); - - common->clk_smi = devm_clk_get(dev, "smi"); - if (IS_ERR(common->clk_smi)) - return PTR_ERR(common->clk_smi); + common->clk_num = ARRAY_SIZE(mtk_smi_common_clocks); + for (i = 0; i < common->clk_num; i++) + common->clks[i].id = mtk_smi_common_clocks[i]; - if (common->plat->has_gals) { - common->clk_gals0 = devm_clk_get(dev, "gals0"); - if (IS_ERR(common->clk_gals0)) - return PTR_ERR(common->clk_gals0); - - common->clk_gals1 = devm_clk_get(dev, "gals1"); - if (IS_ERR(common->clk_gals1)) - return PTR_ERR(common->clk_gals1); - } + ret = devm_clk_bulk_get_optional(dev, common->clk_num, common->clks); + if (ret) + return ret; /* * for mtk smi gen 1, we need to get the ao(always on) base to config @@ -561,11 +507,9 @@ static int __maybe_unused mtk_smi_common_resume(struct device *dev) u32 bus_sel = common->plat->bus_sel; int ret; - ret = mtk_smi_clk_enable(common); - if (ret) { - dev_err(common->dev, "Failed to enable clock(%d).\n", ret); + ret = clk_bulk_prepare_enable(common->clk_num, common->clks); + if (ret) return ret; - } if (common->plat->gen == MTK_SMI_GEN2 && bus_sel) writel(bus_sel, common->base + SMI_BUS_SEL); @@ -576,7 +520,7 @@ static int __maybe_unused mtk_smi_common_suspend(struct device *dev) { struct mtk_smi *common = dev_get_drvdata(dev); - mtk_smi_clk_disable(common); + clk_bulk_disable_unprepare(common->clk_num, common->clks); return 0; } -- 2.18.0