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Thu, 17 Jun 2021 03:14:05 +0000 From: "Peng Fan (OSS)" To: Adam Ford , "Peng Fan (OSS)" CC: Rob Herring , Shawn Guo , Sascha Hauer , Sascha Hauer , Fabio Estevam , dl-linux-imx , Philipp Zabel , Lucas Stach , Krzysztof Kozlowski , =?iso-8859-1?Q?Guido_G=FCnther?= , Marek Vasut , Andrey Smirnov , devicetree , arm-soc , Linux Kernel Mailing List , Jacky Bai , Schrempf Frieder , Abel Vesa Subject: RE: [PATCH V7 4/4] soc: imx: Add blk-ctl driver for i.MX8MM Thread-Topic: [PATCH V7 4/4] soc: imx: Add blk-ctl driver for i.MX8MM Thread-Index: AQHXX4q0hWf55kqEaUikJcAamP0XDqsT0TkAgAAWxgCAAQWlAIABiZQAgAEVUaA= Date: Thu, 17 Jun 2021 03:14:05 +0000 Message-ID: References: <20210612133134.2738-1-peng.fan@oss.nxp.com> <20210612133134.2738-5-peng.fan@oss.nxp.com> <7683ab0b-f905-dff1-aa4f-76ad638da568@oss.nxp.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: gmail.com; dkim=none (message not signed) header.d=none;gmail.com; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AM5PR0402MB2756.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: fef587e7-5410-414d-3815-08d9313df717 X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Jun 2021 03:14:05.6336 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 1tCssBTJGlvJg5O7TrJHK+eqTAsBxXRSBMJU2nmnWbM+xALfnC16u0ZvLbUQu+438ps84mdeJ3Lx2dlMNBr/QQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM5PR04MB3204 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > Subject: Re: [PATCH V7 4/4] soc: imx: Add blk-ctl driver for i.MX8MM >=20 > On Tue, Jun 15, 2021 at 6:05 AM Peng Fan (OSS) > wrote: > > > > > > On 2021/6/15 3:29, Adam Ford wrote: > > > On Mon, Jun 14, 2021 at 1:07 PM Adam Ford > wrote: > > >> > > >> On Sat, Jun 12, 2021 at 7:58 AM Peng Fan (OSS) > wrote: > > >>> > > >>> From: Peng Fan > > >>> > > >>> The i.MX8MM SoC has dispmix BLK-CTL and vpumix BLK-CTL, so we > add > > >>> that support in this driver. > > >>> > > >>> Reviewed-by: Abel Vesa > > >>> Signed-off-by: Peng Fan > > >> > > >> Maybe my TF-A is too old, but I am not able to wake the device from > > >> suspend-to-ram with this series. I used the device tree from [1] > > >> to enable both the GPCv2 and the blk-ctl stuff. > > >> > > >> [1] - > > >> https://eur01.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2F= p > > >> > atchwork.kernel.org%2Fproject%2Flinux-arm-kernel%2Fpatch%2F20210604 > > >> > 111005.6804-1-peng.fan%40oss.nxp.com%2F&data=3D04%7C01%7Cpeng. > fan > > >> %40nxp.com%7C29fe5fa2af704121c2d508d930b25126%7C686ea1d3bc > 2b4c6fa92 > > >> > cd99c5c301635%7C0%7C0%7C637594364693096718%7CUnknown%7CTWF > pbGZsb3d8 > > >> > eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3 > D% > > >> > 7C1000&sdata=3DowV810qvJWHnaoav%2BZDlpd%2FmjALiZkk0uWM44gqj > jQ8%3D > > >> &reserved=3D0 > > >> > > >> I based both off Shawn's for-next branch. > > > > > > I tried to enable USB with the GPCv2 stuff pulled into Shawn's > > > for-next branch, and my board hangs when USB is loaded, but USB > > > doesn't use blk-ctl, it just uses GPCv2. > > > > > > I looked at some of the changes with GPCv2, and I noticed a comment > > > in the GPCv2 function called imx_pgc_power_up. The comment reads: > > > > > > /* > > > * ret =3D regmap_read_poll_timeout(domain->regmap, GPC_PU_PWRHSK, > reg_val, > > > * (reg_val & domain->bits.hskack), 0, > > > * USEC_PER_MSEC); > > > * Technically we need the commented code to wait handshake. But that > > > needs > > > * the BLK-CTL module BUS clk-en bit being set. > > > * > > > * There is a separate BLK-CTL module and we will have such a driver > > > for it, > > > * that driver will set the BUS clk-en bit and handshake will be > > > triggered > > > * automatically there. Just add a delay and suppose the handshake > > > finish > > > * after that. > > > */ > > > > > > I didn't see a delay here despite the comment saying we should add on= e. > > > > > > With the blk-ctl enabled, I attempted to uncomment the above line of > > > code without much success in preventing the board from hanging. > > > > > > If BUS clk-en bit needs to be set in order for the handshake to > > > work, should all these power domains reference it to bring it up? > > > If we decide against using the BUS clk-en bit, what should this delay= be? > > > > It is only for power domain has mix and need delay for the handshake. > > USB no need that handshake. >=20 > Don't the OTG domains depend on hsiomix? It works well with this change in dtsi. diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mm.dtsi index 0e01ff649956..e930ae3122ec 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1087,6 +1087,7 @@ usbotg1: usb@32e40000 { assigned-clock-parents =3D <&clk IMX8MM_SYS= _PLL2_500M>; fsl,usbphy =3D <&usbphynop1>; fsl,usbmisc =3D <&usbmisc1 0>; + power-domains =3D <&pgc_otg1>; status =3D "disabled"; }; @@ -1106,6 +1107,7 @@ usbotg2: usb@32e50000 { assigned-clock-parents =3D <&clk IMX8MM_SYS= _PLL2_500M>; fsl,usbphy =3D <&usbphynop2>; fsl,usbmisc =3D <&usbmisc2 0>; + power-domains =3D <&pgc_otg2>; status =3D "disabled"; }; Regards, Peng. >=20 > > > > Could you post a github branch, then I could give a look? >=20 > No problem. >=20 > https://eur01.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Fgithu= b. > com%2Faford173%2Flinux%2Ftree%2Ffor-next&data=3D04%7C01%7Cpen > g.fan%40nxp.com%7C29fe5fa2af704121c2d508d930b25126%7C686ea1d3bc > 2b4c6fa92cd99c5c301635%7C0%7C0%7C637594364693106714%7CUnknow > n%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1ha > WwiLCJXVCI6Mn0%3D%7C1000&sdata=3D6tiEiL7TMioVeb88WKHTYxVPxE > MT1pboN%2FSMxiKA1yM%3D&reserved=3D0 >=20 > thanks >=20 > adam >=20 > > > > Thanks, > > Peng. > > > > > > > > adam > > >> > > >> adam > > >> > > >>> --- > > >>> drivers/soc/imx/Makefile | 2 +- > > >>> drivers/soc/imx/blk-ctl-imx8mm.c | 139 > +++++++++++++++++++++++++++++++ > > >>> 2 files changed, 140 insertions(+), 1 deletion(-) > > >>> create mode 100644 drivers/soc/imx/blk-ctl-imx8mm.c > > >>> > > >>> diff --git a/drivers/soc/imx/Makefile b/drivers/soc/imx/Makefile > > >>> index d3d2b49a386c..c260b962f495 100644 > > >>> --- a/drivers/soc/imx/Makefile > > >>> +++ b/drivers/soc/imx/Makefile > > >>> @@ -4,4 +4,4 @@ obj-$(CONFIG_ARCH_MXC) +=3D soc-imx.o > > >>> endif > > >>> obj-$(CONFIG_HAVE_IMX_GPC) +=3D gpc.o > > >>> obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) +=3D gpcv2.o > > >>> -obj-$(CONFIG_SOC_IMX8M) +=3D soc-imx8m.o blk-ctl.o > > >>> +obj-$(CONFIG_SOC_IMX8M) +=3D soc-imx8m.o blk-ctl.o > blk-ctl-imx8mm.o > > >>> diff --git a/drivers/soc/imx/blk-ctl-imx8mm.c > > >>> b/drivers/soc/imx/blk-ctl-imx8mm.c > > >>> new file mode 100644 > > >>> index 000000000000..59443588f892 > > >>> --- /dev/null > > >>> +++ b/drivers/soc/imx/blk-ctl-imx8mm.c > > >>> @@ -0,0 +1,139 @@ > > >>> +// SPDX-License-Identifier: GPL-2.0 > > >>> +/* > > >>> + * Copyright 2021 NXP > > >>> + */ > > >>> + > > >>> +#include > > >>> +#include > > >>> +#include > > >>> +#include > > >>> +#include > > >>> +#include > > >>> +#include > > >>> +#include > > >>> +#include > > >>> +#include #include > > >>> +#include #include #include > > >>> + > > >>> + > > >>> +#include "blk-ctl.h" > > >>> + > > >>> +#define MEDIA_BLK_BUS_RSTN_BLK_SYNC_SFT_EN > BIT(6) > > >>> +#define MEDIA_BLK_MIPI_DSI_I_PRESETN_SFT_EN > BIT(5) > > >>> +#define MEDIA_BLK_MIPI_CSI_I_PRESETN_SFT_EN > BIT(4) > > >>> +#define MEDIA_BLK_CAMERA_PIXEL_RESET_N_SFT_EN > BIT(3) > > >>> +#define MEDIA_BLK_CSI_BRIDGE_SFT_EN > GENMASK(2, 0) > > >>> + > > >>> +#define MEDIA_BLK_BUS_PD_MASK > BIT(12) > > >>> +#define MEDIA_BLK_MIPI_CSI_PD_MASK > GENMASK(11, 10) > > >>> +#define MEDIA_BLK_MIPI_DSI_PD_MASK > GENMASK(9, 8) > > >>> +#define MEDIA_BLK_LCDIF_PD_MASK > GENMASK(7, 6) > > >>> +#define MEDIA_BLK_CSI_BRIDGE_PD_MASK > GENMASK(5, 0) > > >>> + > > >>> +static struct imx_blk_ctl_hw imx8mm_dispmix_blk_ctl_pds[] =3D { > > >>> + IMX_BLK_CTL_PD("CSI_BRIDGE", NULL, > IMX8MM_BLK_CTL_PD_DISPMIX_CSI_BRIDGE, 0x4, > > >>> + MEDIA_BLK_CSI_BRIDGE_PD_MASK, 0, > MEDIA_BLK_CSI_BRIDGE_SFT_EN, > > >>> + IMX_BLK_CTL_PD_RESET), > > >>> + IMX_BLK_CTL_PD("LCDIF", NULL, > IMX8MM_BLK_CTL_PD_DISPMIX_LCDIF, 0x4, > > >>> + MEDIA_BLK_LCDIF_PD_MASK, -1, -1, 0), > > >>> + IMX_BLK_CTL_PD("MIPI_DSI", "mipi", > IMX8MM_BLK_CTL_PD_DISPMIX_MIPI_DSI, 0x4, > > >>> + MEDIA_BLK_MIPI_DSI_PD_MASK, 0, > MEDIA_BLK_MIPI_DSI_I_PRESETN_SFT_EN, > > >>> + IMX_BLK_CTL_PD_RESET), > > >>> + IMX_BLK_CTL_PD("MIPI_CSI", "mipi", > IMX8MM_BLK_CTL_PD_DISPMIX_MIPI_CSI, 0x4, > > >>> + MEDIA_BLK_MIPI_CSI_PD_MASK, 0, > > >>> + > MEDIA_BLK_MIPI_CSI_I_PRESETN_SFT_EN | > MEDIA_BLK_CAMERA_PIXEL_RESET_N_SFT_EN, > > >>> + IMX_BLK_CTL_PD_RESET), > > >>> + IMX_BLK_CTL_PD("DISPMIX_BUS", "dispmix", > IMX8MM_BLK_CTL_PD_DISPMIX_BUS, 0x4, > > >>> + MEDIA_BLK_BUS_PD_MASK, 0, > MEDIA_BLK_BUS_RSTN_BLK_SYNC_SFT_EN, > > >>> + IMX_BLK_CTL_PD_HANDSHAKE | > > >>> +IMX_BLK_CTL_PD_RESET) }; > > >>> + > > >>> +static struct imx_blk_ctl_hw imx8mm_vpumix_blk_ctl_pds[] =3D { > > >>> + IMX_BLK_CTL_PD("VPU_BLK_CTL_G2", "vpu-g2", > IMX8MM_BLK_CTL_PD_VPU_G2, 0x4, > > >>> + BIT(0), 0, BIT(0), > IMX_BLK_CTL_PD_RESET), > > >>> + IMX_BLK_CTL_PD("VPU_BLK_CTL_G1", "vpu-g1", > IMX8MM_BLK_CTL_PD_VPU_G1, 0x4, > > >>> + BIT(1), 0, BIT(1), > IMX_BLK_CTL_PD_RESET), > > >>> + IMX_BLK_CTL_PD("VPU_BLK_CTL_H1", "vpu-h1", > IMX8MM_BLK_CTL_PD_VPU_H1, 0x4, > > >>> + BIT(2), 0, BIT(2), > IMX_BLK_CTL_PD_RESET), > > >>> + IMX_BLK_CTL_PD("VPU_BLK_CTL_BUS", "vpumix", > IMX8MM_BLK_CTL_PD_VPU_BUS, 0x4, > > >>> + BIT(2), 0, BIT(2), > IMX_BLK_CTL_PD_HANDSHAKE > > >>> +| IMX_BLK_CTL_PD_RESET) }; > > >>> + > > >>> +static const struct regmap_config imx8mm_blk_ctl_regmap_config =3D= { > > >>> + .reg_bits =3D 32, > > >>> + .reg_stride =3D 4, > > >>> + .val_bits =3D 32, > > >>> + .max_register =3D 0x30, > > >>> + .fast_io =3D true, > > >>> +}; > > >>> + > > >>> +static const struct imx_blk_ctl_dev_data > imx8mm_vpumix_blk_ctl_dev_data =3D { > > >>> + .pds =3D imx8mm_vpumix_blk_ctl_pds, > > >>> + .pds_num =3D ARRAY_SIZE(imx8mm_vpumix_blk_ctl_pds), > > >>> + .max_num =3D IMX8MM_BLK_CTL_PD_VPU_MAX, > > >>> + .hw_hsk =3D &imx8mm_vpumix_blk_ctl_pds[3], > > >>> + .config =3D imx8mm_blk_ctl_regmap_config, > > >>> + .name =3D "imx-vpumix-blk-ctl", }; > > >>> + > > >>> +static const struct imx_blk_ctl_dev_data > imx8mm_dispmix_blk_ctl_dev_data =3D { > > >>> + .pds =3D imx8mm_dispmix_blk_ctl_pds, > > >>> + .pds_num =3D ARRAY_SIZE(imx8mm_dispmix_blk_ctl_pds), > > >>> + .max_num =3D IMX8MM_BLK_CTL_PD_DISPMIX_MAX, > > >>> + .hw_hsk =3D &imx8mm_dispmix_blk_ctl_pds[4], > > >>> + .config =3D imx8mm_blk_ctl_regmap_config, > > >>> + .name =3D "imx-dispmix-blk-ctl", }; > > >>> + > > >>> +static int imx8mm_blk_ctl_probe(struct platform_device *pdev) { > > >>> + struct device *dev =3D &pdev->dev; > > >>> + const struct imx_blk_ctl_dev_data *dev_data =3D > of_device_get_match_data(dev); > > >>> + struct regmap *regmap; > > >>> + struct imx_blk_ctl *ctl; > > >>> + void __iomem *base; > > >>> + > > >>> + ctl =3D devm_kzalloc(dev, sizeof(*ctl), GFP_KERNEL); > > >>> + if (!ctl) > > >>> + return -ENOMEM; > > >>> + > > >>> + base =3D devm_platform_ioremap_resource(pdev, 0); > > >>> + if (IS_ERR(base)) > > >>> + return PTR_ERR(base); > > >>> + > > >>> + regmap =3D devm_regmap_init_mmio(dev, base, > &dev_data->config); > > >>> + if (IS_ERR(regmap)) > > >>> + return PTR_ERR(regmap); > > >>> + > > >>> + ctl->regmap =3D regmap; > > >>> + ctl->dev =3D dev; > > >>> + mutex_init(&ctl->lock); > > >>> + > > >>> + ctl->num_clks =3D devm_clk_bulk_get_all(dev, &ctl->clks); > > >>> + if (ctl->num_clks < 0) > > >>> + return ctl->num_clks; > > >>> + > > >>> + dev_set_drvdata(dev, ctl); > > >>> + ctl->dev_data =3D dev_data; > > >>> + > > >>> + return imx_blk_ctl_register(dev); } > > >>> + > > >>> +static const struct of_device_id imx_blk_ctl_of_match[] =3D { > > >>> + { .compatible =3D "fsl,imx8mm-vpumix-blk-ctl", .data =3D > &imx8mm_vpumix_blk_ctl_dev_data }, > > >>> + { .compatible =3D "fsl,imx8mm-dispmix-blk-ctl", .data =3D > &imx8mm_dispmix_blk_ctl_dev_data }, > > >>> + { /* Sentinel */ } > > >>> +}; > > >>> +MODULE_DEVICE_TABLE(of, imx_blk_ctl_of_match); > > >>> + > > >>> +static struct platform_driver imx_blk_ctl_driver =3D { > > >>> + .probe =3D imx8mm_blk_ctl_probe, > > >>> + .driver =3D { > > >>> + .name =3D "imx8mm-blk-ctl", > > >>> + .of_match_table =3D > of_match_ptr(imx_blk_ctl_of_match), > > >>> + .pm =3D &imx_blk_ctl_pm_ops, > > >>> + }, > > >>> +}; > > >>> +module_platform_driver(imx_blk_ctl_driver); > > >>> -- > > >>> 2.30.0 > > >>>