Received: by 2002:a05:6a10:206:0:0:0:0 with SMTP id 6csp145085pxj; Wed, 16 Jun 2021 22:50:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwkfkcxP+1iQUi93yW1K/QkjUKa8DUQQfv2E4njIGpuD+Cu3QCVC2fHU4/NeB4oSrgcdItV X-Received: by 2002:a17:906:8318:: with SMTP id j24mr3300441ejx.375.1623909002385; Wed, 16 Jun 2021 22:50:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1623909002; cv=none; d=google.com; s=arc-20160816; b=LpW1eHPYp7WVmC2TYCZPNvYqGQECbwF+2nE+jciRh69+/NyBhH/+d2VVVGTrxj75bU jxHlUT42E6PAWjBHkrznLbl+w7Yl7HstbUNDLXyt7B0NszrZjc3VgnwD0ZZitd4wGUHV sUW8ct7jpJr3ELDTeKiBZtfXmVn17OePN1DUpHXuk3scpygYtXRSaUyOjHzNQlkLFfrH Pnj+5OCBJNBjFtN/TYwjRzguEBD1p8ttai1FRXZ5YkiqXbAePL4zFQausgb/n2Y8z81D YctSydA4eSFNSYr0lGuBsOcwZKiHK3EAhgF5/8PpGtbMOMe6FUpkdPeQhNKoUZTGoXqo 7hmg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from; bh=25sPGN8coBdCE2krPEN40oSdd9bFT/m6fOfsLvuGWe0=; b=sA2G5UtTMWBxdmNo9TPivNd42broOYBknlJtNWtZM0Gu40kO6kOr3o++KivzSx9Z58 lX4+Re8ECj1DsMsYLLY0d5H16UXxZs031n9jIJtHJ+LLN0bNPlY30PzoVag1Bfwkoxk4 y8RN4em53Y/CzhjRXKM8Ag1ie1WNmpPzvSD9IaDlZFAsze5b1jUrDVyzzmvq2831Z4Vg 8vqAHt/lr1Xl+EMgUyZx5biH8v31HuGvZPynhWR9cqT+XG2XiCfIdLMi7uvbzsNJn82z F07GOGrSBKy3yOAjCU8mOoYa+W/J7KErA/cM7X7IjAbs3ZfXc4Y7UEFrJTX0L0znG4ca 3xfg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id f21si4522796ejj.567.2021.06.16.22.49.39; Wed, 16 Jun 2021 22:50:02 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229848AbhFQFup (ORCPT + 99 others); Thu, 17 Jun 2021 01:50:45 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:51914 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S229782AbhFQFuo (ORCPT ); Thu, 17 Jun 2021 01:50:44 -0400 X-UUID: 46e6c695761741f19e72e456a70f6893-20210617 X-UUID: 46e6c695761741f19e72e456a70f6893-20210617 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 358933624; Thu, 17 Jun 2021 13:48:34 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 17 Jun 2021 13:48:32 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 17 Jun 2021 13:48:32 +0800 From: Trevor Wu To: , , , CC: , , , , , , , , Subject: [PATCH 1/8] ASoC: mediatek: mt8195: update mediatek common driver Date: Thu, 17 Jun 2021 13:47:32 +0800 Message-ID: <20210617054740.8081-2-trevor.wu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210617054740.8081-1-trevor.wu@mediatek.com> References: <20210617054740.8081-1-trevor.wu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Update mediatek common driver to support MT8195 Signed-off-by: Trevor Wu --- sound/soc/mediatek/common/mtk-afe-fe-dai.c | 20 ++++++++++++++++++-- sound/soc/mediatek/common/mtk-base-afe.h | 10 ++++++++-- 2 files changed, 26 insertions(+), 4 deletions(-) diff --git a/sound/soc/mediatek/common/mtk-afe-fe-dai.c b/sound/soc/mediatek/common/mtk-afe-fe-dai.c index 3cb2adf420bb..cdede0172534 100644 --- a/sound/soc/mediatek/common/mtk-afe-fe-dai.c +++ b/sound/soc/mediatek/common/mtk-afe-fe-dai.c @@ -433,11 +433,20 @@ int mtk_memif_set_addr(struct mtk_base_afe *afe, int id, phys_buf_addr_upper_32); } - /* set MSB to 33-bit */ - if (memif->data->msb_reg >= 0) + /* + * set MSB to 33-bit, for memif address + * only for memif base address, if msb_end_reg exists + */ + if (memif->data->msb_reg) mtk_regmap_update_bits(afe->regmap, memif->data->msb_reg, 1, msb_at_bit33, memif->data->msb_shift); + /* set MSB to 33-bit, for memif end address */ + if (memif->data->msb_end_reg) + mtk_regmap_update_bits(afe->regmap, memif->data->msb_end_reg, + 1, msb_at_bit33, + memif->data->msb_end_shift); + return 0; } EXPORT_SYMBOL_GPL(mtk_memif_set_addr); @@ -464,6 +473,13 @@ int mtk_memif_set_channel(struct mtk_base_afe *afe, else mono = (channel == 1) ? 1 : 0; + /* for specific configuration of memif mono mode */ + if (memif->data->int_odd_flag_reg) + mtk_regmap_update_bits(afe->regmap, + memif->data->int_odd_flag_reg, + 1, mono, + memif->data->int_odd_flag_shift); + return mtk_regmap_update_bits(afe->regmap, memif->data->mono_reg, 1, mono, memif->data->mono_shift); } diff --git a/sound/soc/mediatek/common/mtk-base-afe.h b/sound/soc/mediatek/common/mtk-base-afe.h index a6f68c68581c..ef83e78c22a8 100644 --- a/sound/soc/mediatek/common/mtk-base-afe.h +++ b/sound/soc/mediatek/common/mtk-base-afe.h @@ -29,6 +29,8 @@ struct mtk_base_memif_data { int quad_ch_reg; int quad_ch_mask; int quad_ch_shift; + int int_odd_flag_reg; + int int_odd_flag_shift; int enable_reg; int enable_shift; int hd_reg; @@ -37,10 +39,13 @@ struct mtk_base_memif_data { int hd_align_mshift; int msb_reg; int msb_shift; - int msb2_reg; - int msb2_shift; + int msb_end_reg; + int msb_end_shift; int agent_disable_reg; int agent_disable_shift; + int ch_num_reg; + int ch_num_shift; + int ch_num_maskbit; /* playback memif only */ int pbuf_reg; int pbuf_mask; @@ -62,6 +67,7 @@ struct mtk_base_irq_data { int irq_en_shift; int irq_clr_reg; int irq_clr_shift; + int irq_status_shift; }; struct device; -- 2.18.0