Received: by 2002:a05:6a10:206:0:0:0:0 with SMTP id 6csp1641372pxj; Fri, 18 Jun 2021 11:29:00 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxXxEm3DWmHtJhJQVP0riP7J21W+AMzoLo0ozrEwdndxnRsyyzKrZs9s4v1l9fb6C99WBn5 X-Received: by 2002:a6b:7714:: with SMTP id n20mr8638627iom.126.1624040940742; Fri, 18 Jun 2021 11:29:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624040940; cv=none; d=google.com; s=arc-20160816; b=hJmkqcnPBQBGVzpklwgKFo0icuPFBer6pr8gB0hzXqV/OKsaLjV/VMkXQI42tNwx7u TDKr/7PLJrDMLcfm0/2zVWFFRIE4sk7j7INTYpZf6iVIQM3HNxkGx6oMG/R9OSnvEdiP 68G/887maJbpu/cX9ugAfZjXtDbG9kCVZPeCDyiqxUcyN1rrM0SfC/9X+dm+D0+41FLP uDGHnG9vMEMBswNJiTvIkvbEK0NfWwkh9OoRoiC8AOc92WAXW/xG3VzkcPMQgEv3GpWL aK01NtQsJWhmhiLSXYTqUtyfyJ2nljaMB+ZmUCmRS+JiSokERikrjza9esnRs6pj/2P5 ncEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:ironport-sdr:ironport-sdr; bh=Rk1CmrAIwM1geRBWZ/jjHgegbRfZjq2fXBk7lT2hTO8=; b=P/2Erb6NOtmEYyyeP4vbQfBVhmKW57bzNKndQ66stRcfG/eAcnGUQBxFr81b99w6mS cB8kCY5Xe0KU0R/oW26Uc4Pe1+epZI55QmFvWXPhCdfDm6bWMrviFfZ7izV5PgcPyfne 6KlqcyBgOZEgJsIETQWKS4p33IRRG0CHJVLt+12Qg6c0Vd+X3u8KFkHoaPNcBzNqQ+zt tDZ97LE8reEv2wXp0Cc9q0ZBYsFVlIhW5DMsg3dKeQOy0wr4UyNmosumiP6Izvn5gtxX ZA+dapgT61LVSRKe3hA+Hf0S2AiWXTc4gtgohNgVrBcsl80DHdL6+Et0gtDARTntaGfW 2W/Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id l18si10421021jak.5.2021.06.18.11.28.48; Fri, 18 Jun 2021 11:29:00 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235546AbhFRPcQ (ORCPT + 99 others); Fri, 18 Jun 2021 11:32:16 -0400 Received: from mga01.intel.com ([192.55.52.88]:7103 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235285AbhFRPb2 (ORCPT ); Fri, 18 Jun 2021 11:31:28 -0400 IronPort-SDR: MgQ5ZCxjNAFS7/vz0kphj771n7b1AugnoPbXZd2t75njCz+5yuxf4+pHRysSA6Ya93YmzjFJy4 XAWNFhnIsu2Q== X-IronPort-AV: E=McAfee;i="6200,9189,10019"; a="228099639" X-IronPort-AV: E=Sophos;i="5.83,284,1616482800"; d="scan'208";a="228099639" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jun 2021 08:27:38 -0700 IronPort-SDR: r8HS9NGeR6AV/PCqnu0qtWuyQ4OrVqc1qFvOvO1v+K3Y7Cnl5BNYtJapsKTskIEujVzKl+tTia q9m/u86F77+A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.83,284,1616482800"; d="scan'208";a="405004810" Received: from otc-lr-04.jf.intel.com ([10.54.39.41]) by orsmga006.jf.intel.com with ESMTP; 18 Jun 2021 08:27:32 -0700 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, linux-kernel@vger.kernel.org Cc: acme@kernel.org, jolsa@redhat.com, namhyung@kernel.org, ak@linux.intel.com, Kan Liang , stable@vger.kernel.org Subject: [PATCH 2/3] perf/x86/intel: Add more events requires FRONTEND MSR on Sapphire Rapids Date: Fri, 18 Jun 2021 08:12:53 -0700 Message-Id: <1624029174-122219-3-git-send-email-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1624029174-122219-1-git-send-email-kan.liang@linux.intel.com> References: <1624029174-122219-1-git-send-email-kan.liang@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Kan Liang On Sapphire Rapids, there are two more events 0x40ad and 0x04c2 which rely on the FRONTEND MSR. If the FRONTEND MSR is not set correctly, the count value is not correct. Update intel_spr_extra_regs[] to support them. Fixes: 61b985e3e775 ("perf/x86/intel: Add perf core PMU support for Sapphire Rapids") Signed-off-by: Kan Liang Cc: stable@vger.kernel.org --- arch/x86/events/intel/core.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index d39991b..e442b55 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -280,6 +280,8 @@ static struct extra_reg intel_spr_extra_regs[] __read_mostly = { INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), + INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE), + INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE), EVENT_EXTRA_END }; -- 2.7.4