Received: by 2002:a05:6a10:206:0:0:0:0 with SMTP id 6csp1684536pxj; Fri, 18 Jun 2021 12:36:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz5bNVSPX/XFSE0fTckW3MbJLTaKRmoFEp/vzVUE30XiK/Enpbo8u2SAfw5bltm9r5xQ1Hy X-Received: by 2002:a17:906:6d95:: with SMTP id h21mr12724243ejt.260.1624044989748; Fri, 18 Jun 2021 12:36:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624044989; cv=none; d=google.com; s=arc-20160816; b=eLBPunp862J0OdQHa2NkO6238DdRvDIwUeZLTihQxM9cFm0Po0zaDOF0fHsZItFrG6 EOxlhOPcVhd8DLNoWEQb3DymfBOAt7e1TSwdvKMU8SwlJIsTAVdUXhgEoR8xeMs2JHCr 0X/20UtMk118W/M/cC031rQYdRRmyQdzn6f2XN2iZS0yGtg7WxNt/0oQlGezyGNAHD4k oD/O4+zFik/K4VJipOBdl1XHoispsnfzjwjcPoP7Jv8Ol0uCUcliZkvEq8Q9Zex4wgJp ohM3hqsltcDx5H5J75b2UrNKdj2JLO3nAzbvGRV+dME5SYo1rndiehoQsJ4f/+1kkbsU Xl1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:in-reply-to:content-disposition:mime-version :references:message-id:subject:cc:to:from:date:dkim-signature; bh=7nPUjc8QA8UoxeQQWsD1UQARcs1YVj1sKwBdqRAk8Q8=; b=Mo/P/3pseCBvF4yPxOPvntq1wCd2qn/AQKfY7sWYY4WpZMEMr7+ipcX61CpfaCBfdO zjiP5mMFPpGkaBkFch8v8TBMBsCstitMMic75lS3d2fS7PPH2/FhqVmC9Tk/WMltfkq1 rUJWQ8KYr/kq7DNdxk7xfZrYb4biLluXRUY/3UXYng27LEdAX4UXqyIo0jJia++zbQaI yiXecGXTReOXAdnB3k35KMtQf4U3VajO4QDOzwqpKuBUSD+p0Wq9EqTpXln0wSYf2HOi r6pXnuPUujf+JEMKDfFeY9tGlg2I+2SQB+yKhLBBGgsNk/MQnxhVs3Op+CF8lYTTuKbN QwJQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PHiVcGzV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id u5si3492487ejn.571.2021.06.18.12.36.05; Fri, 18 Jun 2021 12:36:29 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PHiVcGzV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235079AbhFRSSw (ORCPT + 99 others); Fri, 18 Jun 2021 14:18:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40454 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232392AbhFRSSv (ORCPT ); Fri, 18 Jun 2021 14:18:51 -0400 Received: from mail-oi1-x234.google.com (mail-oi1-x234.google.com [IPv6:2607:f8b0:4864:20::234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B3071C061574 for ; Fri, 18 Jun 2021 11:16:41 -0700 (PDT) Received: by mail-oi1-x234.google.com with SMTP id t40so11470020oiw.8 for ; Fri, 18 Jun 2021 11:16:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=7nPUjc8QA8UoxeQQWsD1UQARcs1YVj1sKwBdqRAk8Q8=; b=PHiVcGzVJuHJlg20MflDvGrcV6QmQqNDQPo1eXlcu0MkkFtxNyjn/o4p5oCK6CQ98y qvsuDygUlGKFnIHlmDQ7SmgVxktLOCFAeqtlGXmiWlJia9u5L8pzgrv6ZNT40hGdlGjU Jhk9eMCcOeNK0Sn86SmZgLAJDo3gtoQCDSxtnvePgM6VNT7R+4xZW/zvTTGbv3XQKySp gbJ6CguaXCVTsvr/xNFhoCFq7ZqIAkAH7zZ+A+M259FRh1hOxtnmt0ioYcFSHXCuruZS FikDCXnejHBAVd+SUz4O1uh1QDDAXv5z2lUNxBnNi38OfWZ+TeOIftu3gwv+9NCOyYEY 87MA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=7nPUjc8QA8UoxeQQWsD1UQARcs1YVj1sKwBdqRAk8Q8=; b=EmypOTAvkJtq2mF0rrGmz/Vm9OxF6ZSqaNcO9qzmOEENN4zZpRT1kkJGDxSKIVAKDU vpjVV6UVhdxISoK4i9dt2DnZ6G3dajf/SAH1vGIZFyRv9hEHYTkY5DaJIpQExtAuoSVJ wCOwcxPnadGUyXSne7ix/rHVUPYQG83+UTg+NKo4Sr1pYtb0LBcJYkfPUBAWfPneL72r ldL3eJ633PtixKu+tap9mIkfWo0EShPov1iKs8xRvXzBg3Kf4wQnU8dZwOyU5bfjvcgM sHDNBZ/NFaU3tIKzkkkKeXh7SETxdf3HuMtbhQldfxUBPwFVK55CG4PaibkP766eoi/b 4w7Q== X-Gm-Message-State: AOAM5310QE4x4o4Y6ia6nISB8WcAVRaKwlFqGZ/Eyx1mIvjLfFYSQegF Okj5V3pBYv13Cq1cnbn+igLw58k495aSrg== X-Received: by 2002:a05:6808:1148:: with SMTP id u8mr8092340oiu.125.1624040201036; Fri, 18 Jun 2021 11:16:41 -0700 (PDT) Received: from builder.lan (104-57-184-186.lightspeed.austtx.sbcglobal.net. [104.57.184.186]) by smtp.gmail.com with ESMTPSA id c12sm1949076oov.11.2021.06.18.11.16.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Jun 2021 11:16:40 -0700 (PDT) Date: Fri, 18 Jun 2021 13:16:38 -0500 From: Bjorn Andersson To: Thara Gopinath Cc: agross@kernel.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, viresh.kumar@linaro.org, rjw@rjwysocki.net, robh+dt@kernel.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH 3/5] cpufreq: qcom-cpufreq-hw: Add dcvs interrupt support Message-ID: References: <20210608222926.2707768-1-thara.gopinath@linaro.org> <20210608222926.2707768-4-thara.gopinath@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210608222926.2707768-4-thara.gopinath@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue 08 Jun 17:29 CDT 2021, Thara Gopinath wrote: > diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c [..] > @@ -305,6 +383,8 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) > > index = args.args[0]; > > + lmh_mitigation_enabled = of_property_read_bool(pdev->dev.of_node, "qcom,support-lmh"); Rather than adding a new interrupt _and_ a flag to tell the driver that this new interrupt should be used, wouldn't it be sufficient to just see if the interrupt is specified? > + > res = platform_get_resource(pdev, IORESOURCE_MEM, index); > if (!res) { > dev_err(dev, "failed to get mem resource %d\n", index); > @@ -329,6 +409,11 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) > goto unmap_base; > } > > + if (!alloc_cpumask_var(&data->cpus, GFP_KERNEL)) { > + ret = -ENOMEM; > + goto unmap_base; > + } > + > data->soc_data = of_device_get_match_data(&pdev->dev); > data->base = base; > data->res = res; > @@ -347,6 +432,7 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) > goto error; > } > > + cpumask_copy(data->cpus, policy->cpus); > policy->driver_data = data; > > ret = qcom_cpufreq_hw_read_lut(cpu_dev, policy); > @@ -370,6 +456,20 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) > dev_warn(cpu_dev, "failed to enable boost: %d\n", ret); > } > > + if (lmh_mitigation_enabled) { > + data->lmh_dcvs_irq = platform_get_irq(pdev, index); > + if (data->lmh_dcvs_irq < 0) { This will be -ENXIO if the interrupt isn't specified and <0 for other errors, so you should be able to distinguish the two failure cases. Regards, Bjorn > + ret = data->lmh_dcvs_irq; > + goto error; > + } > + ret = devm_request_irq(dev, data->lmh_dcvs_irq, qcom_lmh_dcvs_handle_irq, > + 0, "dcvsh-irq", data); > + if (ret) { > + dev_err(dev, "Error %d registering irq %x\n", ret, data->lmh_dcvs_irq); > + goto error; > + } > + INIT_DEFERRABLE_WORK(&data->lmh_dcvs_poll_work, qcom_lmh_dcvs_poll); > + } > return 0; > error: > kfree(data); > -- > 2.25.1 >