Received: by 2002:a05:6a10:206:0:0:0:0 with SMTP id 6csp2014018pxj; Sat, 19 Jun 2021 00:05:08 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzjdDvVo2KLgO6SoaMDrtp2LgUC9Cv4VWb6Lt8bgv+rzxa7AlEdDVK6fO/cKzuQPdoS0agO X-Received: by 2002:a02:cab2:: with SMTP id e18mr7147301jap.80.1624086307927; Sat, 19 Jun 2021 00:05:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624086307; cv=none; d=google.com; s=arc-20160816; b=MoYQv15jBEglU85nKUNf7xwnSB6cEEIHzllQPY8kF1gsqjI3xn05qNdk8ZiSjdra+y 8HLfa7jEkU72hMj2ho+pPObP6C7o8HHVS5toUvxLMYYMBYJ1NYo5MtDSjse7dTbGg6sH cugVhXC/hExIUy/ET79/Utc0bPARyj238Phm+ZfkBnwFe0mUBv2LQpIaCvqSddlWXlMe E+zOlArIn6Qmi6bfXBhiRiLwopKUDIWKiSDfw99WvC2ZWEqf0b59eDU+6li9/Ootc6MC 2b9XCdARGobTlMRMO7i5o+w2BhBaf0WgvGiVTxKyOXtYdfpY9aqmSbxzm26shTsvx56c wjvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:message-id:date:subject:cc:to:from:dmarc-filter :sender:dkim-signature; bh=vWuSQFDHY7f5boYAnelARlfd06pI5S2myIc0m2GVLnA=; b=NH2P0tKx8lY6df8rktM11+eRn2CQ8O19q/9kfsOslrMqFv3Hx5rwNasYkLhVH0xcad dPN0uC2jLoaeIxFyckdkTau8ZmV/A5EsbAN61D3TjjcbmK9HRtcSHcVlb/fygNkifxN+ 8Y4tNNEOCI7/SHJ/U/A7ABPzWpHvnbvM3tWunn5j7HQw2z7c7CHNYbklZBDlCEyxt9yQ 03RxU67c31sEmXsgeEQb4413LBxaDDvDm24MgSwngJ7ZCIK98BcCjAHA8/npBSodOsuP nfQx04qHLqwUDcCXR68bJgH1vQ9MlJ9Iv7PMRwS/yj7HcRU5XoYo9+u33q6M2IA5DDI0 7LVw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mg.codeaurora.org header.s=smtp header.b=VYtZGRc8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id r127si11738105iod.92.2021.06.19.00.04.56; Sat, 19 Jun 2021 00:05:07 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@mg.codeaurora.org header.s=smtp header.b=VYtZGRc8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234656AbhFRV5X (ORCPT + 99 others); Fri, 18 Jun 2021 17:57:23 -0400 Received: from so254-9.mailgun.net ([198.61.254.9]:40574 "EHLO so254-9.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232735AbhFRV5W (ORCPT ); Fri, 18 Jun 2021 17:57:22 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1624053312; h=Message-Id: Date: Subject: Cc: To: From: Sender; bh=vWuSQFDHY7f5boYAnelARlfd06pI5S2myIc0m2GVLnA=; b=VYtZGRc8QwP3DCotX85O3WRBDLG0VPRVcn9IoeCT4HwqzMfG6vcLkht+2wfryamjLUIfpZly egN0WEc5iu+iN7dNqd3adGGee27ZdjrB01QdT8+i6a3BTQDCPnE7f0JxOJha9lh47bQ4vuTj gva1m9k0EDpJcswXJENnBJmTOaw= X-Mailgun-Sending-Ip: 198.61.254.9 X-Mailgun-Sid: WyI0MWYwYSIsICJsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n04.prod.us-west-2.postgun.com with SMTP id 60cd163ee570c05619e4a69f (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Fri, 18 Jun 2021 21:55:10 GMT Sender: bbhatt=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 06F44C43217; Fri, 18 Jun 2021 21:55:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=ALL_TRUSTED,BAYES_00,SPF_FAIL, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from malabar-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: bbhatt) by smtp.codeaurora.org (Postfix) with ESMTPSA id 91F59C433D3; Fri, 18 Jun 2021 21:55:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 91F59C433D3 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=bbhatt@codeaurora.org From: Bhaumik Bhatt To: manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, hemantk@codeaurora.org, jhugo@codeaurora.org, linux-kernel@vger.kernel.org, carl.yin@quectel.com, naveen.kumar@quectel.com, loic.poulain@linaro.org, Bhaumik Bhatt Subject: [PATCH v2] bus: mhi: pci_generic: Apply no-op for wake using sideband wake boolean Date: Fri, 18 Jun 2021 14:55:02 -0700 Message-Id: <1624053302-22470-1-git-send-email-bbhatt@codeaurora.org> X-Mailer: git-send-email 2.7.4 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Devices such as SDX24 do not have the provision for inband wake doorbell in the form of channel 127 and instead have a sideband GPIO for it. Newer devices such as SDX55 or SDX65 support inband wake method by default. Ensure the functionality is used based on this such that device wake stays held when a client driver uses mhi_device_get() API or the equivalent debugfs entry. Fixes: e3e5e6508fc1 ("bus: mhi: pci_generic: No-Op for device_wake operations") Signed-off-by: Bhaumik Bhatt --- v2: Use sideband instead of no_inband_wake and update description Tested on: X86_64 architecture with SDX65 device on Ubuntu 18.04 drivers/bus/mhi/pci_generic.c | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index d84b743..56f7107 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -32,6 +32,7 @@ * @edl: emergency download mode firmware path (if any) * @bar_num: PCI base address register to use for MHI MMIO register space * @dma_data_width: DMA transfer word size (32 or 64 bits) + * @sideband_wake: Devices without inband wake support (such as sdx24) */ struct mhi_pci_dev_info { const struct mhi_controller_config *config; @@ -40,6 +41,7 @@ struct mhi_pci_dev_info { const char *edl; unsigned int bar_num; unsigned int dma_data_width; + bool sideband_wake; }; #define MHI_CHANNEL_CONFIG_UL(ch_num, ch_name, el_count, ev_ring) \ @@ -242,7 +244,8 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx65_info = { .edl = "qcom/sdx65m/edl.mbn", .config = &modem_qcom_v1_mhiv_config, .bar_num = MHI_PCI_DEFAULT_BAR_NUM, - .dma_data_width = 32 + .dma_data_width = 32, + .sideband_wake = false }; static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = { @@ -251,7 +254,8 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = { .edl = "qcom/sdx55m/edl.mbn", .config = &modem_qcom_v1_mhiv_config, .bar_num = MHI_PCI_DEFAULT_BAR_NUM, - .dma_data_width = 32 + .dma_data_width = 32, + .sideband_wake = false }; static const struct mhi_pci_dev_info mhi_qcom_sdx24_info = { @@ -259,7 +263,8 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx24_info = { .edl = "qcom/prog_firehose_sdx24.mbn", .config = &modem_qcom_v1_mhiv_config, .bar_num = MHI_PCI_DEFAULT_BAR_NUM, - .dma_data_width = 32 + .dma_data_width = 32, + .sideband_wake = true }; static const struct mhi_channel_config mhi_quectel_em1xx_channels[] = { @@ -301,7 +306,8 @@ static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = { .edl = "qcom/prog_firehose_sdx24.mbn", .config = &modem_quectel_em1xx_config, .bar_num = MHI_PCI_DEFAULT_BAR_NUM, - .dma_data_width = 32 + .dma_data_width = 32, + .sideband_wake = true }; static const struct mhi_channel_config mhi_foxconn_sdx55_channels[] = { @@ -339,7 +345,8 @@ static const struct mhi_pci_dev_info mhi_foxconn_sdx55_info = { .edl = "qcom/sdx55m/edl.mbn", .config = &modem_foxconn_sdx55_config, .bar_num = MHI_PCI_DEFAULT_BAR_NUM, - .dma_data_width = 32 + .dma_data_width = 32, + .sideband_wake = false }; static const struct pci_device_id mhi_pci_id_table[] = { @@ -640,9 +647,12 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) mhi_cntrl->status_cb = mhi_pci_status_cb; mhi_cntrl->runtime_get = mhi_pci_runtime_get; mhi_cntrl->runtime_put = mhi_pci_runtime_put; - mhi_cntrl->wake_get = mhi_pci_wake_get_nop; - mhi_cntrl->wake_put = mhi_pci_wake_put_nop; - mhi_cntrl->wake_toggle = mhi_pci_wake_toggle_nop; + + if (info->sideband_wake) { + mhi_cntrl->wake_get = mhi_pci_wake_get_nop; + mhi_cntrl->wake_put = mhi_pci_wake_put_nop; + mhi_cntrl->wake_toggle = mhi_pci_wake_toggle_nop; + } err = mhi_pci_claim(mhi_cntrl, info->bar_num, DMA_BIT_MASK(info->dma_data_width)); if (err) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project