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[71.163.245.5]) by smtp.gmail.com with ESMTPSA id m3sm2455132qkk.27.2021.06.18.14.55.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 18 Jun 2021 14:55:20 -0700 (PDT) Subject: Re: [PATCH 3/5] cpufreq: qcom-cpufreq-hw: Add dcvs interrupt support To: Bjorn Andersson Cc: agross@kernel.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, viresh.kumar@linaro.org, rjw@rjwysocki.net, robh+dt@kernel.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20210608222926.2707768-1-thara.gopinath@linaro.org> <20210608222926.2707768-4-thara.gopinath@linaro.org> From: Thara Gopinath Message-ID: <4e6f96c0-5f9c-bd35-7b6a-95ac6e907dab@linaro.org> Date: Fri, 18 Jun 2021 17:55:18 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 6/18/21 2:16 PM, Bjorn Andersson wrote: > On Tue 08 Jun 17:29 CDT 2021, Thara Gopinath wrote: >> diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c > [..] >> @@ -305,6 +383,8 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) >> >> index = args.args[0]; >> >> + lmh_mitigation_enabled = of_property_read_bool(pdev->dev.of_node, "qcom,support-lmh"); > > Rather than adding a new interrupt _and_ a flag to tell the driver that > this new interrupt should be used, wouldn't it be sufficient to just see > if the interrupt is specified? Yes. you are right. It should be. Though when I wrote it there was some reason which I forget now. I will remove it. -- Warm Regards Thara (She/Her/Hers) > >> + >> res = platform_get_resource(pdev, IORESOURCE_MEM, index); >> if (!res) { >> dev_err(dev, "failed to get mem resource %d\n", index); >> @@ -329,6 +409,11 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) >> goto unmap_base; >> } >> >> + if (!alloc_cpumask_var(&data->cpus, GFP_KERNEL)) { >> + ret = -ENOMEM; >> + goto unmap_base; >> + } >> + >> data->soc_data = of_device_get_match_data(&pdev->dev); >> data->base = base; >> data->res = res; >> @@ -347,6 +432,7 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) >> goto error; >> } >> >> + cpumask_copy(data->cpus, policy->cpus); >> policy->driver_data = data; >> >> ret = qcom_cpufreq_hw_read_lut(cpu_dev, policy); >> @@ -370,6 +456,20 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) >> dev_warn(cpu_dev, "failed to enable boost: %d\n", ret); >> } >> >> + if (lmh_mitigation_enabled) { >> + data->lmh_dcvs_irq = platform_get_irq(pdev, index); >> + if (data->lmh_dcvs_irq < 0) { > > This will be -ENXIO if the interrupt isn't specified and <0 for other > errors, so you should be able to distinguish the two failure cases. > > Regards, > Bjorn > >> + ret = data->lmh_dcvs_irq; >> + goto error; >> + } >> + ret = devm_request_irq(dev, data->lmh_dcvs_irq, qcom_lmh_dcvs_handle_irq, >> + 0, "dcvsh-irq", data); >> + if (ret) { >> + dev_err(dev, "Error %d registering irq %x\n", ret, data->lmh_dcvs_irq); >> + goto error; >> + } >> + INIT_DEFERRABLE_WORK(&data->lmh_dcvs_poll_work, qcom_lmh_dcvs_poll); >> + } >> return 0; >> error: >> kfree(data); >> -- >> 2.25.1 >>