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From:   Peng Fan <peng.fan@nxp.com>
To:     "Peng Fan (OSS)" <peng.fan@oss.nxp.com>,
        "jassisinghbrar@gmail.com" <jassisinghbrar@gmail.com>,
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CC:     "kernel@pengutronix.de" <kernel@pengutronix.de>,
        "festevam@gmail.com" <festevam@gmail.com>,
        Aisheng Dong <aisheng.dong@nxp.com>,
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Subject: RE: [PATCH V2 0/4] mailbox: imx: add i.MX8ULP MU support
Thread-Topic: [PATCH V2 0/4] mailbox: imx: add i.MX8ULP MU support
Thread-Index: AQHXU6R6K6QSx37q5k+p0a7yiEn/XqsfXa6Q
Date:   Tue, 22 Jun 2021 01:04:00 +0000
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> Subject: [PATCH V2 0/4] mailbox: imx: add i.MX8ULP MU support

Gentle ping..

Thanks,
Peng.

>=20
> From: Peng Fan <peng.fan@nxp.com>
>=20
> V2:
>  Add A-b from Rob in patch 1
>  Fix RXDB for i.MX8ULP in patch 4
>=20
> i.MX8ULP generic MU is a different IP compared with previous i.MX chips.
> It has different register layout and bit position, but the register name =
and bit
> definitions are almost same with previous i.MX MU.
>=20
> So we extend the current imx-mailbox driver to support i.MX8ULP.
>=20
> Peng Fan (4):
>   dt-bindings: mailbox: imx-mu: add i.MX8ULP MU support
>   mailbox: imx: replace the xTR/xRR array with single register
>   mailbox: imx: add xSR/xCR register array
>   mailbox: imx-mailbox: support i.MX8ULP MU
>=20
>  .../devicetree/bindings/mailbox/fsl,mu.yaml   |   1 +
>  drivers/mailbox/imx-mailbox.c                 | 196
> +++++++++++-------
>  2 files changed, 123 insertions(+), 74 deletions(-)
>=20
> --
> 2.30.0