Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
MIME-Version: 1.0
References: <20210617194154.2397-1-linux.amoon@gmail.com> <20210617194154.2397-8-linux.amoon@gmail.com>
 <CAFBinCC0KScn6cJ36ZB_=TRncOOCXJHWwR3s=o3TobH=yOrGJA@mail.gmail.com> <CANAwSgRi7UcS22QKZRRhwYvB3Dyk0ChowX+KByEsxP35ezjtKw@mail.gmail.com>
In-Reply-To: <CANAwSgRi7UcS22QKZRRhwYvB3Dyk0ChowX+KByEsxP35ezjtKw@mail.gmail.com>
From:   Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Date:   Tue, 22 Jun 2021 22:00:50 +0200
Message-ID: <CAFBinCD1+FTx59kVn7w=RurZVK48S3+pdXYjjW_LEQtTEr87mg@mail.gmail.com>
Subject: Re: [RFCv1 7/8] phy: amlogic: meson8b-usb2: Power off the PHY by
 putting it into reset mode.
To:     Anand Moon <linux.amoon@gmail.com>
Cc:     Kishon Vijay Abraham I <kishon@ti.com>,
        Vinod Koul <vkoul@kernel.org>,
        Neil Armstrong <narmstrong@baylibre.com>,
        Kevin Hilman <khilman@baylibre.com>,
        Jerome Brunet <jbrunet@baylibre.com>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        linux-phy@lists.infradead.org,
        linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
        linux-amlogic@lists.infradead.org,
        Linux Kernel <linux-kernel@vger.kernel.org>
Content-Type: text/plain; charset="UTF-8"
Precedence: bulk

Hi Anand,

On Mon, Jun 21, 2021 at 9:15 AM Anand Moon <linux.amoon@gmail.com> wrote:
>
> Hi Martin,
>
> On Fri, 18 Jun 2021 at 04:07, Martin Blumenstingl
> <martin.blumenstingl@googlemail.com> wrote:
> >
> > Hi Anand,
> >
> > On Thu, Jun 17, 2021 at 9:44 PM Anand Moon <linux.amoon@gmail.com> wrote:
> > [...]
> > > @@ -245,8 +250,6 @@ static int phy_meson8b_usb2_power_on(struct phy *phy)
> > >         regmap_update_bits(priv->regmap, REG_CTRL, REG_CTRL_FSEL_MASK,
> > >                            0x5 << REG_CTRL_FSEL_SHIFT);
> > >         /* reset the PHY */
> > > -       regmap_update_bits(priv->regmap, REG_CTRL, REG_CTRL_POWER_ON_RESET,
> > > -                          REG_CTRL_POWER_ON_RESET);
> > The vendor driver uses the following sequence for the power on reset:
> > - set the power on reset bit
> > - wait 500us
> > - clear the power on reset bit
> > - wait 500us
> >
> > With your change we now:
> > - wait 500us
> > - clear the power on reset bit
> > - wait 500us
> >
> > I don't know if this is sufficient to bring the PHY into a well-defined state.
> > Maybe it works, maybe it doesn't reset at all in this case - I don't
> > know how to verify this though.
> >
> Initially, I tried to some bit mask code to resolve this but it failed,
> So no harm in keeping the original changes.
yes, I feel more comfortable with that

> There is another parameter REG_CTRL_PORT_RESET to be considered.
none of the vendor kernels that I have sets or clears this bit explicitly
I agree that the name seems related, but due to lack of an example or
documentation how/when to use this bit I suggest we don't touch it for
now


Best rergards,
Martin