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From:   Gabriel FERNANDEZ <gabriel.fernandez@st.com>
To:     Dario Binacchi <dariobin@libero.it>,
        "linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>
CC:     Alexandre TORGUE - foss <alexandre.torgue@foss.st.com>,
        Maxime Coquelin <mcoquelin.stm32@gmail.com>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "linux-stm32@st-md-mailman.stormreply.com" 
        <linux-stm32@st-md-mailman.stormreply.com>,
        Gabriel FERNANDEZ - foss <gabriel.fernandez@foss.st.com>
Subject: Re: [PATCH] clk: stm32f4: fix post divisor setup for I2S/SAI PLLs
Thread-Topic: [PATCH] clk: stm32f4: fix post divisor setup for I2S/SAI PLLs
Thread-Index: AQHXZ6uOCktfUfYWYk2+Yi5wSfjGMashH4G3
Date:   Wed, 23 Jun 2021 06:27:54 +0000
Message-ID: <AM8PR10MB47856D4CA879CD0230ED171081089@AM8PR10MB4785.EURPRD10.PROD.OUTLOOK.COM>
References: <20210622211401.25604-1-dariobin@libero.it>
In-Reply-To: <20210622211401.25604-1-dariobin@libero.it>
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=0A=
Hi Dario,=0A=
=0A=
I agree with your analyse. =0A=
You have to change also 'u8 pll_num' from 'stm32f4_pll_post_div_data' struc=
ture into 'int pll_idx' =0A=
or something like that.=0A=
Many Thanks !=0A=
Gabriel=0A=
=0A=
=0A=
From: Dario Binacchi <dariobin@libero.it>=0A=
Sent: Tuesday, June 22, 2021 11:14 PM=0A=
To: linux-clk@vger.kernel.org <linux-clk@vger.kernel.org>=0A=
Cc: Dario Binacchi <dariobin@libero.it>; Alexandre TORGUE - foss <alexandre=
.torgue@foss.st.com>; Gabriel FERNANDEZ <gabriel.fernandez@st.com>; Maxime =
Coquelin <mcoquelin.stm32@gmail.com>; Michael Turquette <mturquette@baylibr=
e.com>; Stephen Boyd <sboyd@kernel.org>; linux-arm-kernel@lists.infradead.o=
rg <linux-arm-kernel@lists.infradead.org>; linux-kernel@vger.kernel.org <li=
nux-kernel@vger.kernel.org>; linux-stm32@st-md-mailman.stormreply.com <linu=
x-stm32@st-md-mailman.stormreply.com>=0A=
Subject: [PATCH] clk: stm32f4: fix post divisor setup for I2S/SAI PLLs =0A=
=A0=0A=
Enabling the framebuffer leads to a system hang. Running, as a debug=0A=
hack, the store_pan() function in drivers/video/fbdev/core/fbsysfs.c=0A=
without taking the console_lock, allows to see the crash backtrace on=0A=
the serial line.=0A=
=0A=
~ # echo 0 0 > /sys/class/graphics/fb0/pan=0A=
=0A=
[=A0=A0=A0 9.719414] Unhandled exception: IPSR =3D 00000005 LR =3D fffffff1=
=0A=
[=A0=A0=A0 9.726937] CPU: 0 PID: 49 Comm: sh Not tainted 5.13.0-rc5 #9=0A=
[=A0=A0=A0 9.733008] Hardware name: STM32 (Device Tree Support)=0A=
[=A0=A0=A0 9.738296] PC is at clk_gate_is_enabled+0x0/0x28=0A=
[=A0=A0=A0 9.743426] LR is at stm32f4_pll_div_set_rate+0xf/0x38=0A=
[=A0=A0=A0 9.748857] pc : [<0011e4be>]=A0=A0=A0 lr : [<0011f9e3>]=A0=A0=A0 =
psr: 0100000b=0A=
[=A0=A0=A0 9.755373] sp : 00bc7be0=A0 ip : 00000000=A0 fp : 001f3ac4=0A=
[=A0=A0=A0 9.760812] r10: 002610d0=A0 r9 : 01efe920=A0 r8 : 00540560=0A=
[=A0=A0=A0 9.766269] r7 : 02e7ddb0=A0 r6 : 0173eed8=A0 r5 : 00000000=A0 r4 =
: 004027c0=0A=
[=A0=A0=A0 9.773081] r3 : 0011e4bf=A0 r2 : 02e7ddb0=A0 r1 : 0173eed8=A0 r0 =
: 1d3267b8=0A=
[=A0=A0=A0 9.779911] xPSR: 0100000b=0A=
[=A0=A0=A0 9.782719] CPU: 0 PID: 49 Comm: sh Not tainted 5.13.0-rc5 #9=0A=
[=A0=A0=A0 9.788791] Hardware name: STM32 (Device Tree Support)=0A=
[=A0=A0=A0 9.794120] [<0000afa1>] (unwind_backtrace) from [<0000a33f>] (sho=
w_stack+0xb/0xc)=0A=
[=A0=A0=A0 9.802421] [<0000a33f>] (show_stack) from [<0000a8df>] (__invalid=
_entry+0x4b/0x4c)=0A=
=0A=
The `pll_num' field in the post_div_data configuration contained a wrong=0A=
value which also referenced an uninitialized hardware clock when=0A=
clk_register_pll_div() was called.=0A=
=0A=
Fixes: 517633ef630e ("clk: stm32f4: Add post divisor for I2S & SAI PLLs")=
=0A=
Signed-off-by: Dario Binacchi <dariobin@libero.it>=0A=
=0A=
---=0A=
=0A=
=A0drivers/clk/clk-stm32f4.c | 6 +++---=0A=
=A01 file changed, 3 insertions(+), 3 deletions(-)=0A=
=0A=
diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c=0A=
index 18117ce5ff85..42ca2dd86aea 100644=0A=
--- a/drivers/clk/clk-stm32f4.c=0A=
+++ b/drivers/clk/clk-stm32f4.c=0A=
@@ -557,13 +557,13 @@ static const struct clk_div_table post_divr_table[] =
=3D {=0A=
=A0=0A=
=A0#define MAX_POST_DIV 3=0A=
=A0static const struct stm32f4_pll_post_div_data=A0 post_div_data[MAX_POST_=
DIV] =3D {=0A=
-=A0=A0=A0=A0=A0=A0 { CLK_I2SQ_PDIV, PLL_I2S, "plli2s-q-div", "plli2s-q",=
=0A=
+=A0=A0=A0=A0=A0=A0 { CLK_I2SQ_PDIV, PLL_VCO_I2S, "plli2s-q-div", "plli2s-q=
",=0A=
=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 CLK_SET_RATE_PARENT, STM32=
F4_RCC_DCKCFGR, 0, 5, 0, NULL},=0A=
=A0=0A=
-=A0=A0=A0=A0=A0=A0 { CLK_SAIQ_PDIV, PLL_SAI, "pllsai-q-div", "pllsai-q",=
=0A=
+=A0=A0=A0=A0=A0=A0 { CLK_SAIQ_PDIV, PLL_VCO_SAI, "pllsai-q-div", "pllsai-q=
",=0A=
=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 CLK_SET_RATE_PARENT, STM32=
F4_RCC_DCKCFGR, 8, 5, 0, NULL },=0A=
=A0=0A=
-=A0=A0=A0=A0=A0=A0 { NO_IDX, PLL_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_=
RATE_PARENT,=0A=
+=A0=A0=A0=A0=A0=A0 { NO_IDX, PLL_VCO_SAI, "pllsai-r-div", "pllsai-r", CLK_=
SET_RATE_PARENT,=0A=
=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 STM32F4_RCC_DCKCFGR, 16, 2=
, 0, post_divr_table },=0A=
=A0};=0A=
=A0=0A=
-- =0A=
2.17.1=0A=