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Wed, 23 Jun 2021 07:00:09 -0700 Envelope-to: git@xilinx.com, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, sashal@kernel.org, robh@kernel.org, maz@kernel.org, lorenzo.pieralisi@arm.com, bhelgaas@google.com, monstr@monstr.eu, linux-kernel@vger.kernel.org, kw@linux.com Received: from [172.30.17.109] (port=47614) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1lw3QE-0004mw-Os; Wed, 23 Jun 2021 07:00:07 -0700 Subject: Re: [PATCH v2 2/2] PCI: xilinx-nwl: Enable the clock through CCF To: =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Michal Simek CC: , , , , Hyun Kwon , "Bjorn Helgaas" , Lorenzo Pieralisi , Marc Zyngier , Ravi Kiran Gummaluri , "Rob Herring" , Sasha Levin , , References: <20210623135326.GA54420@rocinante> From: Michal Simek Message-ID: Date: Wed, 23 Jun 2021 16:00:03 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210623135326.GA54420@rocinante> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: be6f0d5f-17db-4643-992b-08d9364f3fc5 X-MS-TrafficTypeDiagnostic: SA0PR02MB7500: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:10000; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: rQikXnoNILhtuuEqFhYxMl7ZhcZmc1YdXQySZx2A/blicUADNuDm2IKBdsOHn7LeUqtC1+t5Lv1EsN7TcsT3oHl8Ih1o2hUqZzvr2EFXzeSl1URt7LGgIchSsBK69wASn2EeBix+MKJHTFUoDkjuRjWPVZSj4olcRQsXWh2JkD6/1fcG2o0WDTF3ciF870A/kI+7FMH74aik0HPAf7jmfK5Su0fI9p/1A5KheJyFqFRgxtwi/OFJ1zIFPLMiIvbEmxjbQZGJDVFfJke8bIiJ/goL3yzBqjPLUlg3FOJLyMMMzLa1MxDAJ5KacOos8PFS8/i6cp+FCrHn5XVGvLYSJYayMyYKhKRzKm+7knxjaBhxs3bnJGbdmwXkT6N22tM/PgPiDBIPPhTTnDFQ/WpANC8zuucp6pz4uk1252iNI4Q/WpR0BLa4Ylh+/lLTVcY70VIaCAZUHr8iIw1IxBOkCVdSQDZERFMGeedaMsBWFP7qSwEu7kcPQwwkjxPzYKozZTyzTrNqOILUNH2NwlBol1p36wm4vJr8qArUgO6KD0AbiWAeezS/GKxlCTt2VhGIE9pccFdrmw1wAYtGh1jYsaeMG7qcKn1NLKz8Hww2kozFmRn18nCPrTHwryhlelsFUgWzOvU3Sbffn+w6trPSe52+ITBqOaxcay/QwOo8mRdaALNwScyZ/VMN80z47WBKPMezSM9AXwSGPMaiFitiiQ== X-Forefront-Antispam-Report: CIP:149.199.62.198;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:xsj-pvapexch01.xlnx.xilinx.com;PTR:unknown-62-198.xilinx.com;CAT:NONE;SFS:(4636009)(136003)(39850400004)(396003)(346002)(376002)(36840700001)(46966006)(8676002)(36756003)(6666004)(8936002)(31696002)(9786002)(31686004)(44832011)(426003)(2616005)(316002)(83380400001)(336012)(82310400003)(36906005)(478600001)(5660300002)(70206006)(70586007)(82740400003)(356005)(110136005)(66574015)(2906002)(7636003)(36860700001)(54906003)(53546011)(186003)(26005)(7416002)(4326008)(47076005)(50156003)(43740500002);DIR:OUT;SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jun 2021 14:00:24.8966 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: be6f0d5f-17db-4643-992b-08d9364f3fc5 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: DM3NAM02FT019.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR02MB7500 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Krzysztof, On 6/23/21 3:53 PM, Krzysztof WilczyƄski wrote: > [+cc Sasha for visibility] > > Hi Michal, > > Thank you for sending v2 so promptly! And for all the extra changes and > fixes. Much appreciated! > >> Enable PCIE reference clock. There is no remove function that's why >> this should be enough for simple operation. >> Normally this clock is enabled by default by firmware but there are >> usecases where this clock should be enabled by driver itself. >> It is also good that clock user is recorded in clock framework. > > Small nitpicks: it would be PCIe here in the above and in the error > message (this is as per [1]), and "use cases" also in the above. > > This can be corrected when the patch will be merged by either Bjorn or > Lorenzo, to avoid sending v3 unnecessarily, provided that they would > have a moment to do it, of course. Ok. Will wait for them. > >> Fixes: ab597d35ef11 ("PCI: xilinx-nwl: Add support for Xilinx NWL PCIe Host Controller") > > Thank you! > > Does it make sense for this change to be back-ported to stable and > long-term kernels? > > I am asking to make sure we do the right thing here, as I can imagine > that older kernels (primarily because some folks could use, for example, > Ubuntu LTS releases for development) might often be used by people who > work with the Xilinx FPGAs and such. I think that make sense to do so. I haven't had a time to take look at it closely but I think on Xilinx ZynqMP zcu102 board this missing patch is causing hang when standard debian 5.10 is used. > > [...] >> + err = clk_prepare_enable(pcie->clk); >> + if (err) { >> + dev_err(dev, "can't enable pcie ref clock\n"); >> + return err; >> + } >> + > > As per the nitpick above, it would be "PCIe", but probably no need to > send v3 to correct this. I will keep my eyes on it and will update it if v3 is required. Thanks, Michal