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Date:   Fri, 25 Jun 2021 09:38:40 +0100
From:   "Russell King (Oracle)" <linux@armlinux.org.uk>
To:     Maxime Chevallier <maxime.chevallier@bootlin.com>
Cc:     Shawn Guo <shawnguo@kernel.org>, Rob Herring <robh+dt@kernel.org>,
        Andrew Lunn <andrew@lunn.ch>, thomas.petazzoni@bootlin.com,
        herve.codina@bootlin.com, devicetree@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] ARM: dts: imx6qdl-sr-som: Increase the PHY reset
 duration to 10ms
Message-ID: <20210625083840.GS22278@shell.armlinux.org.uk>
References: <20210625083051.3691737-1-maxime.chevallier@bootlin.com>
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Sender: Russell King (Oracle) <linux@armlinux.org.uk>
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On Fri, Jun 25, 2021 at 10:30:51AM +0200, Maxime Chevallier wrote:
> The datasheet for the AR803x PHY present on this SoM recommends that the
> reset line is asserted low for 10ms, so that the PHY has time to
> properly reset the internal blocks.
> 
> The previous value of 2ms was found to be problematic on some setups,
> causing intermittent issues where the PHY would be unresponsive
> every once in a while on some sytems, with a low occurence (it typically
> took around 30 consecutive reboots to encounter the issue).
> 
> Bumping the delay to the 10ms recommended value makes the issue
> dissapear, with more than 2500 consecutive reboots performed without the
> issue showing-up.

This isn't actually what the datasheet says, which is:

  Input clock including the crystal and external input clock should be
  stable for at least 1ms before RESET can be deasserted.

  When using crystal, the clock is generated internally after power is
  stable. For a reliable power on reset, suggest to keep asserting the
  reset low long enough (10ms) to ensure the clock is stable and
  clock-to-reset 1ms requirement is satisfied.

The 10ms duration you quote is the _power on reset_ duration, and in
those circumstances, there is a delay before the required clocks will
be stable.

This is not a power on reset scenario - the power was applied long ago
by the time the kernel starts booting, and XI clock would have been
running.

So, I think the commit message which seems to be claiming that the reset
line always needs to be asserted for 10ms is not entirely accurate.

> 
> Fixes: 208d7baf8085 ("ARM: imx: initial SolidRun HummingBoard support")
> Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
> Tested-by: Herv? Codina <herve.codina@bootlin.com>
> ---
>  arch/arm/boot/dts/imx6qdl-sr-som.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/imx6qdl-sr-som.dtsi b/arch/arm/boot/dts/imx6qdl-sr-som.dtsi
> index 0ad8ccde0cf8..a54dafce025b 100644
> --- a/arch/arm/boot/dts/imx6qdl-sr-som.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl-sr-som.dtsi
> @@ -54,7 +54,7 @@ &fec {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
>  	phy-mode = "rgmii-id";
> -	phy-reset-duration = <2>;
> +	phy-reset-duration = <10>;
>  	phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
>  	status = "okay";
>  
> -- 
> 2.25.4
> 
> 

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