Received: by 2002:a05:6a10:f3d0:0:0:0:0 with SMTP id a16csp1024144pxv; Fri, 25 Jun 2021 03:51:31 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwcrIS6a6NpY/1tvJz6Pxb48XvdjhVbbtz9vLfNz6oPfX79BmP9e1M63zHweKmb00d/x2AM X-Received: by 2002:a5d:9ec2:: with SMTP id a2mr7833568ioe.102.1624618291611; Fri, 25 Jun 2021 03:51:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624618291; cv=none; d=google.com; s=arc-20160816; b=iZObQVRpVYCLfLl0uO8uHtyHILLHB3Id3LfKFIqMBQxCq1akJNBQ3soZcHBrumIy7X pvLMU5Vvb6oYx/fxb5MNFAzgLD9WMixEoqqOKZUsqj5ZrnzGTE+yTtwSHHGnGbZAjyZ6 kP//1PxH7SnblLKRB52GWhue91af1WlfWugmRfbqGDCaMBZX0dZcN85emh/ApXa/Q4xq MSFHNjXwX+c5DMMDaCJo+pIpNe2Lgs4RBnIjiCGkB23tQJOznUDWyqsf1M7vERkS2rYl ZN8GQ0e1uN1Ob01qk9LmzPUfB4xRF+y98aQZsxvn5mYxcFTNEMHVsgx9T86DeGRmOIC9 0+/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=GwLTc8NgTA8Bm+bwuBifHsRwrah5oZ7uu4ZqYlPDlU4=; b=c3mzGZR/TmgKI5uZambfe+2/cVt36vDluS/Bb3fCfzxZfstafI4fAtgTd4I57YERLB +R5AL8GXhskWNt3pegsi0uRSaI6QMThBAu8pCUDP0k8DU14e3O3fFSOyFtUidR7U3Q6y 04xkJk6pRwjrpS9/8OI274YOGLqbPVzJAQ3NsuuZKdSM5RcDXSTSr59AkjV9e5qycEZD O2L7D651hIiD+j0ANHaaH5oeHnICvzBWgvBOarZd9CoSw2l1PfCWRtqzSk3LfFXNEGJs sVZc2w0guBKjF7kaKsGX5BD+aspRi3yNBU0RR4oo53fmZnHtkgbSqBhRTFk8IyZgO7lv +m8g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=crapouillou.net Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id n6si5903715ilj.66.2021.06.25.03.51.18; Fri, 25 Jun 2021 03:51:31 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=crapouillou.net Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231563AbhFYKwC (ORCPT + 99 others); Fri, 25 Jun 2021 06:52:02 -0400 Received: from aposti.net ([89.234.176.197]:36628 "EHLO aposti.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229956AbhFYKwB (ORCPT ); Fri, 25 Jun 2021 06:52:01 -0400 From: Paul Cercueil To: Thomas Bogendoerfer Cc: list@opendingux.net, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, Paul Cercueil , stable@vger.kernel.org Subject: [PATCH] MIPS: MT extensions are not available on MIPS32r1 Date: Fri, 25 Jun 2021 11:49:29 +0100 Message-Id: <20210625104929.42689-1-paul@crapouillou.net> In-Reply-To: <202106192349.LlB9JRTC-lkp@intel.com> References: <202106192349.LlB9JRTC-lkp@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org MIPS MT extensions were added with the MIPS 34K processor, which was based on the MIPS32r2 ISA. This fixes a build error when building a generic kernel for a MIPS32r1 CPU. Fixes: c434b9f80b09 ("MIPS: Kconfig: add MIPS_GENERIC_KERNEL symbol") Cc: stable@vger.kernel.org # v5.9 Signed-off-by: Paul Cercueil --- arch/mips/include/asm/cpu-features.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 78cf7e300f12..f98892fd8f1d 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -64,6 +64,8 @@ ((MIPS_ISA_REV >= (ge)) && (MIPS_ISA_REV < (lt))) #define __isa_range_or_flag(ge, lt, flag) \ (__isa_range(ge, lt) || ((MIPS_ISA_REV < (lt)) && __isa(flag))) +#define __isa_range_and_ase(ge, lt, ase) \ + (__isa_range(ge, lt) && __ase(ase)) /* * SMP assumption: Options of CPU 0 are a superset of all processors. @@ -426,7 +428,7 @@ #endif #ifndef cpu_has_mipsmt -#define cpu_has_mipsmt __isa_lt_and_ase(6, MIPS_ASE_MIPSMT) +#define cpu_has_mipsmt __isa_range_and_ase(2, 6, MIPS_ASE_MIPSMT) #endif #ifndef cpu_has_vp -- 2.30.2