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Subject: Re: [PATCH] clk: qcom: ipq8074: fix PCI-E clock oops
From:   Stephen Boyd <sboyd@kernel.org>
Cc:     Robert Marko <robimarko@gmail.com>
To:     Robert Marko <robimarko@gmail.com>, agross@kernel.org,
        bjorn.andersson@linaro.org, linux-arm-msm@vger.kernel.org,
        linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
        mturquette@baylibre.com, sivaprak@codeaurora.org,
        speriaka@codeaurora.org
Date:   Sun, 27 Jun 2021 17:07:29 -0700
Message-ID: <162483884998.3259633.3733659727822681631@swboyd.mtv.corp.google.com>
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Quoting Robert Marko (2021-05-18 10:51:53)
> Fix PCI-E clock related kernel oops that are causes by missing
> parent_names.
>=20
> Without the use of parent_names kernel will panic on
> clk_core_get_parent_by_index() due to a NULL pointer.
>=20
> Without this earlycon is needed to even catch the OOPS as it will reset
> the board before serial is initialized.

Can you share the oops message here in the commit text?

>=20
> Fixes: f0cfcf1ade20 ("clk: qcom: ipq8074: Add missing clocks for pcie")
> Signed-off-by: Robert Marko <robimarko@gmail.com>
> ---
>  drivers/clk/qcom/gcc-ipq8074.c | 11 +++++------
>  1 file changed, 5 insertions(+), 6 deletions(-)
>=20
> diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq807=
4.c
> index 0c619ed35c82..8d8b1717a203 100644
> --- a/drivers/clk/qcom/gcc-ipq8074.c
> +++ b/drivers/clk/qcom/gcc-ipq8074.c
> @@ -4357,8 +4357,7 @@ static struct clk_rcg2 pcie0_rchng_clk_src =3D {
>         .parent_map =3D gcc_xo_gpll0_map,
>         .clkr.hw.init =3D &(struct clk_init_data){
>                 .name =3D "pcie0_rchng_clk_src",
> -               .parent_hws =3D (const struct clk_hw *[]) {
> -                               &gpll0.clkr.hw },
> +               .parent_names =3D gcc_xo_gpll0,

This seems to imply that we need to have two parents but we didn't
realize that was the case. Ouch! Please use a struct clk_parent_data
array and then use the firmware name for XO and the clk_hw pointer for
gpll0.

>                 .num_parents =3D 2,
>                 .ops =3D &clk_rcg2_ops,
>         },
> @@ -4372,8 +4371,8 @@ static struct clk_branch gcc_pcie0_rchng_clk =3D {
>                 .enable_mask =3D BIT(1),
>                 .hw.init =3D &(struct clk_init_data){
>                         .name =3D "gcc_pcie0_rchng_clk",
> -                       .parent_hws =3D (const struct clk_hw *[]){
> -                               &pcie0_rchng_clk_src.clkr.hw,
> +                       .parent_names =3D (const char *[]){
> +                               "pcie0_rchng_clk_src",
>                         },
>                         .num_parents =3D 1,
>                         .flags =3D CLK_SET_RATE_PARENT,
> @@ -4390,8 +4389,8 @@ static struct clk_branch gcc_pcie0_axi_s_bridge_clk=
 =3D {
>                 .enable_mask =3D BIT(0),
>                 .hw.init =3D &(struct clk_init_data){
>                         .name =3D "gcc_pcie0_axi_s_bridge_clk",
> -                       .parent_hws =3D (const struct clk_hw *[]){
> -                               &pcie0_axi_clk_src.clkr.hw,
> +                       .parent_names =3D (const char *[]){
> +                               "pcie0_axi_clk_src"

These two hunks can be dropped.