Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: quoted-printable
In-Reply-To: <20210423004057.283926-3-liambeguin@gmail.com>
References: <20210423004057.283926-1-liambeguin@gmail.com> <20210423004057.283926-3-liambeguin@gmail.com>
Subject: Re: [PATCH v5 2/3] clk: lmk04832: add support for digital delay
From:   Stephen Boyd <sboyd@kernel.org>
Cc:     julia.lawall@inria.fr, linux-clk@vger.kernel.org,
        linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
        robh+dt@kernel.org
To:     liambeguin@gmail.com, mturquette@baylibre.com
Date:   Sun, 27 Jun 2021 18:10:58 -0700
Message-ID: <162484265822.3259633.1205812088952427742@swboyd.mtv.corp.google.com>
User-Agent: alot/0.9.1
Precedence: bulk

Quoting Liam Beguin (2021-04-22 17:40:56)
> From: Liam Beguin <lvb@xiphos.com>
>=20
> The digital delay allows outputs to be delayed from 8 to 1023 VCO
> cycles. The delay step can be as small as half the period of the clock
> distribution path. For example, a 3.2-GHz VCO frequency results in
> 156.25-ps steps.  The digital delay value takes effect on the clock
> output phase after a SYNC event.
>=20
> This is required to support JESD204B subclass 1.
>=20
> Signed-off-by: Liam Beguin <lvb@xiphos.com>
> ---

Applied to clk-next