Received: by 2002:a05:6a10:f3d0:0:0:0:0 with SMTP id a16csp3119476pxv; Sun, 27 Jun 2021 19:40:25 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwYzXMFn68OAid1xrsJYSs8g59pntax6ma1hkSm0/kNWvOr86K2W4LhlaXK2XV9w5f6LYMc X-Received: by 2002:a05:6602:146:: with SMTP id v6mr19231096iot.5.1624848025031; Sun, 27 Jun 2021 19:40:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624848025; cv=none; d=google.com; s=arc-20160816; b=bJe1Nw1QaMfXbeiWxkVWtwrkckUlOIy9Uovfmg1Q2zMoh8xG0l20n1M8M7JPn7bfvb kJOrUPoARgnNmQr8iJndFx/ZaNekOcBHVEQ2PRdT1khttS7TK1rvnkBRc21vd91oD6tZ sQb2vHAoxyrjxR4+zjbCTR1o8dQ+c4N1b4DlyJGbCzb9FKzGu6B6BLDS1mZBpbz4BbKF H8D1gRL58zWgwSgU1AxlC1WksbcyGNItzVurGNvBaB93s1iU6fYuxh3d/RMaAjxkgLxe sV4JuAvoXOl3qsgVFh1Lt4j/GTqNXi/AAzv2ddbitXxhkACcJpcuwH/diIdFe6S5z2rb p06A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:user-agent:message-id:date:to:cc:from:subject :references:in-reply-to:content-transfer-encoding:mime-version :dkim-signature; bh=PL6wa/YJj8LYXRFRWu6+Fojkgd5Bz0KabzHxrtGLc9Y=; b=aMjX9C63G7lTUbPFcm1k8WrgszVK1oMM3bZDvZ92eYqFO2JBKR60MxdZNXQlixT7ao j/wuOHKEV6piAKJWVucbOCxfoR5QUg4ZT0Yg6AIhe1JTE8SnXc138O51CAMfk3Rg/F1e CF0SeRx+FDYhBb19VlrGGBXwZW6A//m3KFIu+zBvblEjkjitkeMKW/U4GhkWHHSAuMAf zWut/3IlNP4pIwyB4W8hAeUKW9WpKfBapXBZkIHJ+5dz8RTeBdUG6cixW18fxFWCae87 /P4EjqDeZ4NPIgoe5L8TO2CF1TgC9q2t/5z3Sq3WNP8ZI4gcUhwmlrKaHq8fxiLnwzOf 3laQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=JKIEBR2o; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id d198si15688658jac.70.2021.06.27.19.40.12; Sun, 27 Jun 2021 19:40:25 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=JKIEBR2o; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231996AbhF1CmI (ORCPT + 99 others); Sun, 27 Jun 2021 22:42:08 -0400 Received: from mail.kernel.org ([198.145.29.99]:53994 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231678AbhF1CmI (ORCPT ); Sun, 27 Jun 2021 22:42:08 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 3EFB4619C4; Mon, 28 Jun 2021 02:39:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1624847983; bh=SoCGeNG9HsDyxEtp2GU2WZmjAAPuhOGmCHPhhj60muU=; h=In-Reply-To:References:Subject:From:Cc:To:Date:From; b=JKIEBR2oQ9Uw+5+bfI1dRTWaB6ZUaiPcjiM+R1JnW5iWgLzXii3r0qdYEMoGCKVbQ Z6zHPO1HRGvE9t8h6WAiAxvfs1llnO5STQhj5wxIZ3gsE/FuRE3yhl7aPg9cJ0zaWA K4lm5rKgALzdaW0zO0iy/7swammUSOK5H5dhEJ/plzMkxVUVyrA55j5sNgdhzE5bnu Vf9N+zBOhkTEd3ilJyQYF5iYuR2zWtTmUFwnnF+brjWadYyLQ90lj5mj6d4bsX6CDJ buDcY2PbucRx0Y09LG1Donz/cBC1tozXuN4se0s8lTRHsQFhwpwiTvgLyee248n5qU DAd0bUCLz+yWw== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable In-Reply-To: <56f3b0bd-5dd7-80d4-041a-0fd2daf4b1f2@marek.ca> References: <20210519001802.1863-1-jonathan@marek.ca> <20210519001802.1863-2-jonathan@marek.ca> <162266925581.4130789.10178141366818328902@swboyd.mtv.corp.google.com> <56f3b0bd-5dd7-80d4-041a-0fd2daf4b1f2@marek.ca> Subject: Re: [PATCH v2 2/2] dt-bindings: clock: add QCOM SM8350 display clock bindings From: Stephen Boyd Cc: Rob Herring , Andy Gross , Bjorn Andersson , Michael Turquette , Rob Herring , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org To: Jonathan Marek , linux-arm-msm@vger.kernel.org Date: Sun, 27 Jun 2021 19:39:41 -0700 Message-ID: <162484798199.3259633.9009940760433821881@swboyd.mtv.corp.google.com> User-Agent: alot/0.9.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Quoting Jonathan Marek (2021-06-04 10:25:41) > On 6/2/21 5:27 PM, Stephen Boyd wrote: > > Quoting Jonathan Marek (2021-05-18 17:18:02) > >> Add sm8350 DISPCC bindings, which are simply a symlink to the sm8250 > >> bindings. Update the documentation with the new compatible. > >> > >> Signed-off-by: Jonathan Marek > >> Reviewed-by: Rob Herring > >> --- > >> .../devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml | 6 ++++= -- > >> include/dt-bindings/clock/qcom,dispcc-sm8350.h | 1 + > >=20 > >> 2 files changed, 5 insertions(+), 2 deletions(-) > >> create mode 120000 include/dt-bindings/clock/qcom,dispcc-sm8350.h > >=20 > > Why the symlink? Can we have the dt authors use the existing header file > > instead? > >=20 >=20 > It would be strange to include bindings with the name of a different=20 > SoC. I guess it is a matter a preference, is there any good reason to=20 > *not* do it like this? $ find include/dt-bindings -type l include/dt-bindings/input/linux-event-codes.h include/dt-bindings/clock/qcom,dispcc-sm8150.h It seems to not be common at all. >=20 > >> > >> diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x5= 0.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml > >> index 0cdf53f41f84..8f414642445e 100644 > >> --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml > >> +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml > >> @@ -4,24 +4,26 @@ > >> $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml# > >> $schema: http://devicetree.org/meta-schemas/core.yaml# > >> =20 > >> -title: Qualcomm Display Clock & Reset Controller Binding for SM8150/S= M8250 > >> +title: Qualcomm Display Clock & Reset Controller Binding for SM8150/S= M8250/SM8350 > >=20 > > Maybe just "Binding for SM8x50 SoCs" > >=20 >=20 > Its likely these bindings won't be compatible with future "SM8x50" SoCs, = > listing supported SoCs explicitly will avoid confusion in the future. The yaml file has sm8x50 in the name. What's the plan there?