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Mon, 28 Jun 2021 00:02:04 -0700 Envelope-to: mturquette@baylibre.com, sboyd@kernel.org, lee.jones@linaro.org, kristo@kernel.org, quanyang.wang@windriver.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Received: from [172.19.2.91] (port=42476 helo=xsjjollys50.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1lxlHP-0000Ik-Vx; Mon, 28 Jun 2021 00:02:04 -0700 From: Rajan Vaja To: , , , , , CC: , , , Rajan Vaja Subject: [PATCH v6 4/4] clk: zynqmp: Handle divider specific read only flag Date: Mon, 28 Jun 2021 00:01:22 -0700 Message-ID: <20210628070122.26217-5-rajan.vaja@xilinx.com> X-Mailer: git-send-email 2.32.0.93.g670b81a In-Reply-To: <20210628070122.26217-1-rajan.vaja@xilinx.com> References: <20210628070122.26217-1-rajan.vaja@xilinx.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f2ab5f23-bc3e-4b0c-9d61-08d93a02a335 X-MS-TrafficTypeDiagnostic: CH2PR02MB6056: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:489; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Jun 2021 07:02:05.1381 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f2ab5f23-bc3e-4b0c-9d61-08d93a02a335 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0013.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR02MB6056 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for divider specific read only CCF flag (CLK_DIVIDER_READ_ONLY). Signed-off-by: Rajan Vaja --- drivers/clk/zynqmp/divider.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c index c07423e03bc8..cb49281f9cf9 100644 --- a/drivers/clk/zynqmp/divider.c +++ b/drivers/clk/zynqmp/divider.c @@ -256,6 +256,11 @@ static const struct clk_ops zynqmp_clk_divider_ops = { .set_rate = zynqmp_clk_divider_set_rate, }; +static const struct clk_ops zynqmp_clk_divider_ro_ops = { + .recalc_rate = zynqmp_clk_divider_recalc_rate, + .round_rate = zynqmp_clk_divider_round_rate, +}; + /** * zynqmp_clk_get_max_divisor() - Get maximum supported divisor from firmware. * @clk_id: Id of clock @@ -334,7 +339,10 @@ struct clk_hw *zynqmp_clk_register_divider(const char *name, return ERR_PTR(-ENOMEM); init.name = name; - init.ops = &zynqmp_clk_divider_ops; + if (nodes->type_flag & CLK_DIVIDER_READ_ONLY) + init.ops = &zynqmp_clk_divider_ro_ops; + else + init.ops = &zynqmp_clk_divider_ops; init.flags = zynqmp_clk_map_common_ccf_flags(nodes->flag); -- 2.32.0.93.g670b81a