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Subject: Re: [PATCH V7 4/4] soc: imx: Add blk-ctl driver for i.MX8MM
To:     Adam Ford <aford173@gmail.com>,
        "Peng Fan (OSS)" <peng.fan@oss.nxp.com>
Cc:     Rob Herring <robh+dt@kernel.org>, Shawn Guo <shawnguo@kernel.org>,
        Sascha Hauer <s.hauer@pengutronix.de>,
        Sascha Hauer <kernel@pengutronix.de>,
        Fabio Estevam <festevam@gmail.com>,
        NXP Linux Team <linux-imx@nxp.com>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Lucas Stach <l.stach@pengutronix.de>,
        Krzysztof Kozlowski <krzk@kernel.org>,
        =?UTF-8?Q?Guido_G=c3=bcnther?= <agx@sigxcpu.org>,
        Andrey Smirnov <andrew.smirnov@gmail.com>,
        devicetree <devicetree@vger.kernel.org>,
        arm-soc <linux-arm-kernel@lists.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Jacky Bai <ping.bai@nxp.com>,
        Schrempf Frieder <frieder.schrempf@kontron.de>,
        Abel Vesa <abel.vesa@nxp.com>, Peng Fan <peng.fan@nxp.com>
References: <20210612133134.2738-1-peng.fan@oss.nxp.com>
 <20210612133134.2738-5-peng.fan@oss.nxp.com>
 <CAHCN7x+bCVcfgb-MmOApBgM=69rz0G8WhsU171SHF3H-12wSfw@mail.gmail.com>
From:   Marek Vasut <marex@denx.de>
Message-ID: <2c39672b-780a-8e33-038e-0856e32ede7a@denx.de>
Date:   Mon, 28 Jun 2021 12:59:31 +0200
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On 6/14/21 8:07 PM, Adam Ford wrote:
> On Sat, Jun 12, 2021 at 7:58 AM Peng Fan (OSS) <peng.fan@oss.nxp.com> wrote:
>>
>> From: Peng Fan <peng.fan@nxp.com>
>>
>> The i.MX8MM SoC has dispmix BLK-CTL and vpumix BLK-CTL, so we add
>> that support in this driver.
>>
>> Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
>> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> 
> Maybe my TF-A is too old, but I am not able to wake the device from
> suspend-to-ram with this series.  I used the device tree from [1] to
> enable both the GPCv2 and the blk-ctl stuff.
> 
> [1] - https://patchwork.kernel.org/project/linux-arm-kernel/patch/20210604111005.6804-1-peng.fan@oss.nxp.com/
> 
> I based both off Shawn's for-next branch.

I also ran into issues with this, although it could also be related to 
GPCv2. On MX8MM , the system sometimes hangs when bringing up the GPCv2 
power domain 6 (VPUMIX). It seems that the GPCv2 driver sets 
GPC_PU_PGC_SW_PUP_REQ register to 0x100 to bring up the VPUMIX and the 
bit never self-clears. After that, it seems the entire GPC locks up. 
Have you ever seen that kind of behavior ?