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Subject: Re: [PATCH] x86/perf: Fixed kernel panic during boot on Nano
 processor.
To:     <peterz@infradead.org>, <mingo@redhat.com>, <acme@kernel.org>,
        <mark.rutland@arm.com>, <alexander.shishkin@linux.intel.com>,
        <jolsa@redhat.com>, <namhyung@kernel.org>, <tglx@linutronix.de>,
        <bp@alien8.de>, <hpa@zytor.com>, <x86@kernel.org>
CC:     <linux-perf-users@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <shyaololo@163.com>, <8vvbbqzo567a@nospam.xutrox.com>
References: <20210607013109.7870-1-CodyYao-oc@zhaoxin.com>
From:   Codyyao-oc <Codyyao-oc@zhaoxin.com>
Message-ID: <174219f5-c8ab-0ee4-8055-5cfa60c6a0fc@zhaoxin.com>
Date:   Wed, 30 Jun 2021 12:38:27 +0800
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Dear Mingo and Peter,

Thank you for taking your precious time to read this letter, I am very 
graterful.


Last month, I fixed the bug that boot failed on Nano processor which 
introduced by

"Fixes: 3a4ac121c2ca ("x86/perf: Add hardware performance events support 
for Zhaoxin CPU.")"

with Arjan's help and submitted this patch.  But I haven't got back. 
Greatly appreciate if you could kindly

check it and reply at your convenience.

Many Thanks!

Cody

On 2021/6/7 上午9:31, Cody Yao-oc wrote:
> From: CodyYao-oc <CodyYao-oc@zhaoxin.com>
>
> Nano processor may not fully support rdpmc instruction, it works well
> for reading general pmc counter, but will lead to GP(general protection)
> when accessing fixed pmc counter. Futhermore, family/model information
> is same between Nano processor and ZX-C processor, it leads to zhaoxin
> pmu driver is wrongly loaded for Nano processor, which resulting boot
> kernal fail.
>
> To solve this problem, stepping information will be checked to distinguish
> between Nano processor and ZX-C processor.
>
> [https://bugzilla.kernel.org/show_bug.cgi?id=212389]
>
> Reported-by: Arjan <8vvbbqzo567a@nospam.xutrox.com>
> Signed-off-by: CodyYao-oc <CodyYao-oc@zhaoxin.com>
> ---
>   arch/x86/events/zhaoxin/core.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/events/zhaoxin/core.c b/arch/x86/events/zhaoxin/core.c
> index 949d845c922b..cef1de251613 100644
> --- a/arch/x86/events/zhaoxin/core.c
> +++ b/arch/x86/events/zhaoxin/core.c
> @@ -541,7 +541,8 @@ __init int zhaoxin_pmu_init(void)
>   
>   	switch (boot_cpu_data.x86) {
>   	case 0x06:
> -		if (boot_cpu_data.x86_model == 0x0f || boot_cpu_data.x86_model == 0x19) {
> +		if ((boot_cpu_data.x86_model == 0x0f && boot_cpu_data.x86_stepping >= 0x0e) ||
> +			boot_cpu_data.x86_model == 0x19) {
>   
>   			x86_pmu.max_period = x86_pmu.cntval_mask >> 1;
>