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[89.6.132.55]) by smtp.gmail.com with ESMTPSA id h10sm5930905wmb.40.2021.06.30.03.53.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 30 Jun 2021 03:53:43 -0700 (PDT) Subject: Re: [PATCH 03/22] clk: mediatek: Fix corner case of tuner_en_reg To: Chen-Yu Tsai , Chun-Jie Chen Cc: Stephen Boyd , Nicolas Boichat , Rob Herring , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, srv_heupstream@mediatek.com, Project_Global_Chrome_Upstream_Group@mediatek.com References: <20210616224743.5109-1-chun-jie.chen@mediatek.com> <20210616224743.5109-4-chun-jie.chen@mediatek.com> From: Matthias Brugger Message-ID: Date: Wed, 30 Jun 2021 12:53:42 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.10.2 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 30/06/2021 09:31, Chen-Yu Tsai wrote: > On Thu, Jun 17, 2021 at 7:01 AM Chun-Jie Chen > wrote: >> >> On MT8195, tuner_en_reg is moved to register offest 0x0. >> If we only judge by tuner_en_reg, it may lead to wrong address. >> Add tuner_en_bit to the check condition. And it has been confirmed, >> on all the MediaTek SoCs, bit0 of offset 0x0 is always occupied by >> clock square control. >> >> Signed-off-by: Chun-Jie Chen > > Reviewed-by: Chen-Yu Tsai > > Though you might want to consider converting these types of checks into feature > flags. > Yes I think adding a feature flag is the way to go. Luckily there are only a few SoCs that will need updates at the same time. Regards, Matthias