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Subject: Re: [PATCH 03/22] clk: mediatek: Fix corner case of tuner_en_reg
To:     Chen-Yu Tsai <wenst@chromium.org>
Cc:     Chun-Jie Chen <chun-jie.chen@mediatek.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Nicolas Boichat <drinkcat@chromium.org>,
        Rob Herring <robh+dt@kernel.org>,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org,
        devicetree@vger.kernel.org, srv_heupstream@mediatek.com,
        Project_Global_Chrome_Upstream_Group@mediatek.com
References: <20210616224743.5109-1-chun-jie.chen@mediatek.com>
 <20210616224743.5109-4-chun-jie.chen@mediatek.com>
 <CAGXv+5F2zTcqnjH2ud38vUD149KJtgxhPQME2Mk6-vGtQv+2YQ@mail.gmail.com>
 <ff6179e8-06f9-fbba-c704-a74381c2149a@gmail.com>
 <CAGXv+5FXuMnhsnytLYKKA9YE97bps7KnkDNADvv8f_wdTqnrfg@mail.gmail.com>
From:   Matthias Brugger <matthias.bgg@gmail.com>
Message-ID: <be824462-4c2f-3bde-0a3d-c5470a5b0fbb@gmail.com>
Date:   Wed, 30 Jun 2021 13:43:18 +0200
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On 30/06/2021 13:09, Chen-Yu Tsai wrote:
> On Wed, Jun 30, 2021 at 6:53 PM Matthias Brugger <matthias.bgg@gmail.com> wrote:
>>
>>
>>
>> On 30/06/2021 09:31, Chen-Yu Tsai wrote:
>>> On Thu, Jun 17, 2021 at 7:01 AM Chun-Jie Chen
>>> <chun-jie.chen@mediatek.com> wrote:
>>>>
>>>> On MT8195, tuner_en_reg is moved to register offest 0x0.
>>>> If we only judge by tuner_en_reg, it may lead to wrong address.
>>>> Add tuner_en_bit to the check condition. And it has been confirmed,
>>>> on all the MediaTek SoCs, bit0 of offset 0x0 is always occupied by
>>>> clock square control.
>>>>
>>>> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
>>>
>>> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
>>>
>>> Though you might want to consider converting these types of checks into feature
>>> flags.
>>>
>>
>> Yes I think adding a feature flag is the way to go. Luckily there are only a few
>> SoCs that will need updates at the same time.
> 
> I also see that the different clock modules are tied together using only clock
> names written in the drivers, instead of clock references in the device tree.
> 

Not sure I understand what you mean. Do you refer to something like [1]? That's
because the clock is probed by the DRM driver, as they share the same compatible
and IP block.

Regards,
Matthias

[1]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/mediatek/clk-mt8173-mm.c?h=v5.13#n139

> Unfortunately reworking this would likely require a lot more work. I previously
> did a bit of internal reworking for the sunxi drivers. While not the same, I
> think the plumbing required is comparable.
> 
> ChenYu
>