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Subject: Re: [PATCH] mmc: sdhci-pci-gli: Finetune GL9763E L1 Entry Delay
To:     Renius Chen <reniuschengl@gmail.com>, ulf.hansson@linaro.org
Cc:     linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org,
        Ben.Chuang@genesyslogic.com.tw
References: <20210624025647.101387-1-reniuschengl@gmail.com>
From:   Adrian Hunter <adrian.hunter@intel.com>
Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki,
 Business Identity Code: 0357606 - 4, Domiciled in Helsinki
Message-ID: <bfa4fbcc-df3e-21e7-b6d8-0f4ae35f0196@intel.com>
Date:   Wed, 30 Jun 2021 15:19:54 +0300
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On 24/06/21 5:56 am, Renius Chen wrote:
> Finetune the L1 entry delay to 20us for better balance of performance and
> battery life.
> 
> Signed-off-by: Renius Chen <reniuschengl@gmail.com>

Acked-by: Adrian Hunter <adrian.hunter@intel.com>

> ---
>  drivers/mmc/host/sdhci-pci-gli.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
> index 302a7579a9b3..4e3c0561354d 100644
> --- a/drivers/mmc/host/sdhci-pci-gli.c
> +++ b/drivers/mmc/host/sdhci-pci-gli.c
> @@ -90,7 +90,7 @@
>  
>  #define PCIE_GLI_9763E_CFG2      0x8A4
>  #define   GLI_9763E_CFG2_L1DLY     GENMASK(28, 19)
> -#define   GLI_9763E_CFG2_L1DLY_MID 0x54
> +#define   GLI_9763E_CFG2_L1DLY_MID 0x50
>  
>  #define PCIE_GLI_9763E_MMC_CTRL  0x960
>  #define   GLI_9763E_HS400_SLOW     BIT(3)
> @@ -810,7 +810,7 @@ static void gli_set_gl9763e(struct sdhci_pci_slot *slot)
>  
>  	pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value);
>  	value &= ~GLI_9763E_CFG2_L1DLY;
> -	/* set ASPM L1 entry delay to 21us */
> +	/* set ASPM L1 entry delay to 20us */
>  	value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MID);
>  	pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value);
>  
>