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From:   Chun-Kuang Hu <chunkuang.hu@kernel.org>
Date:   Thu, 1 Jul 2021 06:48:42 +0800
Message-ID: <CAAOTY_-VAvKCkBj1q4euWFcmbnNUJfXpG9rh9vua80yrok-y9w@mail.gmail.com>
Subject: Re: [PATCH 3/6] arm64: dts: mt8173: Add the mmsys reset bit to reset
 the dsi0
To:     Enric Balletbo i Serra <enric.balletbo@collabora.com>
Cc:     linux-kernel <linux-kernel@vger.kernel.org>,
        Jitao Shi <jitao.shi@mediatek.com>,
        Chun-Kuang Hu <chunkuang.hu@kernel.org>,
        Matthias Brugger <matthias.bgg@gmail.com>,
        Nicolas Boichat <drinkcat@chromium.org>,
        Eizan Miyamoto <eizan@chromium.org>,
        Collabora Kernel ML <kernel@collabora.com>,
        "moderated list:ARM/Mediatek SoC support" 
        <linux-mediatek@lists.infradead.org>,
        Hsin-Yi Wang <hsinyi@chromium.org>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Rob Herring <robh+dt@kernel.org>,
        DTML <devicetree@vger.kernel.org>,
        Linux ARM <linux-arm-kernel@lists.infradead.org>
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HI, Enric:

Enric Balletbo i Serra <enric.balletbo@collabora.com> =E6=96=BC 2021=E5=B9=
=B46=E6=9C=8830=E6=97=A5 =E9=80=B1=E4=B8=89 =E4=B8=8B=E5=8D=8810:47=E5=AF=
=AB=E9=81=93=EF=BC=9A
>
> Reset the DSI hardware is needed to prevent different settings between
> the bootloader and the kernel.
>
> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
> ---
>
>  arch/arm64/boot/dts/mediatek/mt8173.dtsi  | 2 ++
>  include/dt-bindings/reset/mt8173-resets.h | 2 ++
>  2 files changed, 4 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/d=
ts/mediatek/mt8173.dtsi
> index e5596fe01a1d..36c3998eb7f1 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -1036,6 +1036,7 @@ mmsys: syscon@14000000 {
>                         assigned-clocks =3D <&topckgen CLK_TOP_MM_SEL>;
>                         assigned-clock-rates =3D <400000000>;
>                         #clock-cells =3D <1>;
> +                       #reset-cells =3D <1>;
>                         mboxes =3D <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
>                                  <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
>                         mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX=
 0 0x1000>;
> @@ -1262,6 +1263,7 @@ dsi0: dsi@1401b000 {
>                                  <&mmsys CLK_MM_DSI0_DIGITAL>,
>                                  <&mipi_tx0>;
>                         clock-names =3D "engine", "digital", "hs";
> +                       resets =3D <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DS=
I0>;

Add this in binding document. It would be good if the binding document
is in yaml format.

Regards,
Chun-Kuang.

>                         phys =3D <&mipi_tx0>;
>                         phy-names =3D "dphy";
>                         status =3D "disabled";
> diff --git a/include/dt-bindings/reset/mt8173-resets.h b/include/dt-bindi=
ngs/reset/mt8173-resets.h
> index ba8636eda5ae..6a60c7cecc4c 100644
> --- a/include/dt-bindings/reset/mt8173-resets.h
> +++ b/include/dt-bindings/reset/mt8173-resets.h
> @@ -27,6 +27,8 @@
>  #define MT8173_INFRA_GCE_FAXI_RST       40
>  #define MT8173_INFRA_MMIOMMURST         47
>
> +/* MMSYS resets */
> +#define MT8173_MMSYS_SW0_RST_B_DISP_DSI0       25
>
>  /*  PERICFG resets */
>  #define MT8173_PERI_UART0_SW_RST        0
> --
> 2.30.2
>