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Date:   Sat, 3 Jul 2021 17:22:18 +0200
From:   Pavel Machek <pavel@denx.de>
To:     Sasha Levin <sashal@kernel.org>
Cc:     linux-kernel@vger.kernel.org, stable@vger.kernel.org,
        Esben Haabendal <esben@geanix.com>,
        "David S . Miller" <davem@davemloft.net>
Subject: Re: [PATCH 5.10 055/101] net: ll_temac: Add memory-barriers for TX
 BD access
Message-ID: <20210703152218.GD3004@amd>
References: <20210628142607.32218-1-sashal@kernel.org>
 <20210628142607.32218-56-sashal@kernel.org>
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Hi!

> Add a couple of memory-barriers to ensure correct ordering of read/write
> access to TX BDs.

So... this is dealing with CPU-to-device consistency, not CPU-to-CPU,
right?

> +++ b/drivers/net/ethernet/xilinx/ll_temac_main.c
> @@ -774,12 +774,15 @@ static void temac_start_xmit_done(struct net_device=
 *ndev)
>  	stat =3D be32_to_cpu(cur_p->app0);
> =20
>  	while (stat & STS_CTRL_APP0_CMPLT) {
> +		/* Make sure that the other fields are read after bd is
> +		 * released by dma
> +		 */
> +		rmb();
>  		dma_unmap_single(ndev->dev.parent,

Full barrier, as expected.

> @@ -788,6 +791,12 @@ static void temac_start_xmit_done(struct net_device =
*ndev)
>  		ndev->stats.tx_packets++;
>  		ndev->stats.tx_bytes +=3D be32_to_cpu(cur_p->len);
> =20
> +		/* app0 must be visible last, as it is used to flag
> +		 * availability of the bd
> +		 */
> +		smp_mb();

SMP-only barrier, but full barrier is needed here AFAICT.

								Pavel
--=20
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


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