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[23.128.96.18]) by mx.google.com with ESMTP id i12si8900606jal.25.2021.07.03.20.12.01; Sat, 03 Jul 2021 20:12:12 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229991AbhGDDJs (ORCPT + 99 others); Sat, 3 Jul 2021 23:09:48 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:52650 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S229788AbhGDDJl (ORCPT ); Sat, 3 Jul 2021 23:09:41 -0400 X-UUID: e1fa8d53519d413db0fa0bf49d3a5373-20210704 X-UUID: e1fa8d53519d413db0fa0bf49d3a5373-20210704 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 2108483404; Sun, 04 Jul 2021 11:07:03 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 4 Jul 2021 11:07:01 +0800 Received: from mtksdaap41.mediatek.inc (172.21.77.4) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sun, 4 Jul 2021 11:07:01 +0800 From: Hsin-Hsiung Wang To: Stephen Boyd , Rob Herring , Matthias Brugger CC: Hsin-Hsiung Wang , , , , , , Subject: [PATCH v9 2/5] dt-bindings: spmi: document binding for the Mediatek SPMI controller Date: Sun, 4 Jul 2021 11:06:55 +0800 Message-ID: <1625368018-17505-3-git-send-email-hsin-hsiung.wang@mediatek.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1625368018-17505-1-git-send-email-hsin-hsiung.wang@mediatek.com> References: <1625368018-17505-1-git-send-email-hsin-hsiung.wang@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This adds documentation for the SPMI controller found on Mediatek SoCs. Signed-off-by: Hsin-Hsiung Wang --- changes since v8: - Add MT8195 compatible name for spmi support. --- .../bindings/spmi/mtk,spmi-mtk-pmif.yaml | 76 +++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml diff --git a/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml b/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml new file mode 100644 index 000000000000..a221cc1ac6c6 --- /dev/null +++ b/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spmi/mtk,spmi-mtk-pmif.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek SPMI Controller Device Tree Bindings + +maintainers: + - Hsin-Hsiung Wang + +description: |+ + On MediaTek SoCs the PMIC is connected via SPMI and the controller allows + for multiple SoCs to control a single SPMI master. + +allOf: + - $ref: "spmi.yaml" + +properties: + compatible: + enum: + - mediatek,mt6873-spmi + - mediatek,mt8195-spmi + + reg: + maxItems: 2 + + reg-names: + items: + - const: pmif + - const: spmimst + + clocks: + minItems: 3 + maxItems: 3 + + clock-names: + items: + - const: pmif_sys_ck + - const: pmif_tmr_ck + - const: spmimst_clk_mux + + assigned-clocks: + maxItems: 1 + + assigned-clock-parents: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + + spmi: spmi@10027000 { + compatible = "mediatek,mt6873-spmi"; + reg = <0 0x10027000 0 0x000e00>, + <0 0x10029000 0 0x000100>; + reg-names = "pmif", "spmimst"; + clocks = <&infracfg CLK_INFRA_PMIC_AP>, + <&infracfg CLK_INFRA_PMIC_TMR>, + <&topckgen CLK_TOP_SPMI_MST_SEL>; + clock-names = "pmif_sys_ck", + "pmif_tmr_ck", + "spmimst_clk_mux"; + assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; + }; +... -- 2.18.0