Received: by 2002:a05:6a10:f3d0:0:0:0:0 with SMTP id a16csp3474391pxv; Sun, 4 Jul 2021 20:45:46 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwjTLpEmqQY8q9fcKrbAALBTQyV2Bo8/7gZ/SphIHY+It3JBT6qK4ZileTi0kkOxomKoC+l X-Received: by 2002:a17:906:1487:: with SMTP id x7mr11197597ejc.456.1625456746659; Sun, 04 Jul 2021 20:45:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1625456746; cv=none; d=google.com; s=arc-20160816; b=fwvZIPqk+j8SIND0pxNFaGtcJf6NM8mtPy+UnrB1al0jYaQPkWb1jsIHfTYkaAkLcg dN4HrLcdEtSGF4PL0DuJRjJwy4+ErEOUYOCIyuQBoBbnWZWDsIY8AGqJVRSHbzrWGxvx dO8Fecu3DZ3Kje8o5Q83V6/waAtiSnLiRUgfgqq7/DU+aXBKzhUbjIGPeHoJxA2dbzH9 6IH71Nsh9rA2f3Rxru5zz8Ozqq1+8VHsTmq8F52XF9Ln0xMIvtAgd92xdXRNbltp/+DU EaK19DqJwoHuLNjui/wgBsb3VDKkrWrt7BQ9MJEKUZrrbG2E/iMu03QseQXcEWNe87QO VPxA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from; bh=DnbY4tP/z3d8Q2SFw6da18ofk4ABh8NINjbmoRA0JoM=; b=yu6x8SwAf1WAa1arXI5rnHPxS4dJLwxM5wduNMpCpfEmQ+5ov1AegtUsTOhPa2jOvg twXLOApuEabRp54/gTHKoCQ6BrNIuU9NturkxM6/uQ6jqEaR5ge9VHInMuzWVYz5iOQH M8+ZcXtHKadEeLcNMUnZezKp58wP9c0Lmh0pYMDMS4q2mmxjHpBCDzmcVmTosMH7xzEi 5Fw6t7AvmQ4v7okQ7YGZ5qEnuzz8Iucxpa+MQyzu14G4TtTTEe21aWTwXrGwCJLWobF3 7NGLThyb5p6WBXndJBU1EVnPTVm6Z+kRopNid7ClJz4ASSxOLx6WFmNOha2wItvnTByh MRBQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id hc15si6792215ejc.305.2021.07.04.20.45.24; Sun, 04 Jul 2021 20:45:46 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230132AbhGEDpE (ORCPT + 99 others); Sun, 4 Jul 2021 23:45:04 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:47783 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S230138AbhGEDo5 (ORCPT ); Sun, 4 Jul 2021 23:44:57 -0400 X-UUID: c415cd2735af4bb49bfebebb9cf3eef6-20210705 X-UUID: c415cd2735af4bb49bfebebb9cf3eef6-20210705 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1698847864; Mon, 05 Jul 2021 11:42:17 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 5 Jul 2021 11:42:16 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 5 Jul 2021 11:42:15 +0800 From: Chun-Jie Chen To: Matthias Brugger , Stephen Boyd , Nicolas Boichat , Rob Herring CC: , , , , , , , Weiyi Lu , Chun-Jie Chen Subject: [v12 18/20] clk: mediatek: Add MT8192 scp adsp clock support Date: Mon, 5 Jul 2021 11:38:22 +0800 Message-ID: <20210705033824.1934-19-chun-jie.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210705033824.1934-1-chun-jie.chen@mediatek.com> References: <20210705033824.1934-1-chun-jie.chen@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add MT8192 scp adsp clock provider Signed-off-by: Weiyi Lu Signed-off-by: Chun-Jie Chen --- drivers/clk/mediatek/Kconfig | 6 +++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8192-scp_adsp.c | 50 ++++++++++++++++++++++ 3 files changed, 57 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8192-scp_adsp.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 88b24f74aff2..eb4aa29d8106 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -562,6 +562,12 @@ config COMMON_CLK_MT8192_MSDC help This driver supports MediaTek MT8192 msdc and msdc_top clocks. +config COMMON_CLK_MT8192_SCP_ADSP + bool "Clock driver for MediaTek MT8192 scp_adsp" + depends on COMMON_CLK_MT8192 + help + This driver supports MediaTek MT8192 scp_adsp clocks. + config COMMON_CLK_MT8516 bool "Clock driver for MediaTek MT8516" depends on ARCH_MEDIATEK || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 8e4e343d4af4..a336fe753e9a 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -77,5 +77,6 @@ obj-$(CONFIG_COMMON_CLK_MT8192_MDPSYS) += clk-mt8192-mdp.o obj-$(CONFIG_COMMON_CLK_MT8192_MFGCFG) += clk-mt8192-mfg.o obj-$(CONFIG_COMMON_CLK_MT8192_MMSYS) += clk-mt8192-mm.o obj-$(CONFIG_COMMON_CLK_MT8192_MSDC) += clk-mt8192-msdc.o +obj-$(CONFIG_COMMON_CLK_MT8192_SCP_ADSP) += clk-mt8192-scp_adsp.o obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o diff --git a/drivers/clk/mediatek/clk-mt8192-scp_adsp.c b/drivers/clk/mediatek/clk-mt8192-scp_adsp.c new file mode 100644 index 000000000000..58725d79dd13 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8192-scp_adsp.c @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// Copyright (c) 2021 MediaTek Inc. +// Author: Chun-Jie Chen + +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include + +static const struct mtk_gate_regs scp_adsp_cg_regs = { + .set_ofs = 0x180, + .clr_ofs = 0x180, + .sta_ofs = 0x180, +}; + +#define GATE_SCP_ADSP(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &scp_adsp_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) + +static const struct mtk_gate scp_adsp_clks[] = { + GATE_SCP_ADSP(CLK_SCP_ADSP_AUDIODSP, "scp_adsp_audiodsp", "adsp_sel", 0), +}; + +static const struct mtk_clk_desc scp_adsp_desc = { + .clks = scp_adsp_clks, + .num_clks = ARRAY_SIZE(scp_adsp_clks), +}; + +static const struct of_device_id of_match_clk_mt8192_scp_adsp[] = { + { + .compatible = "mediatek,mt8192-scp_adsp", + .data = &scp_adsp_desc, + }, { + /* sentinel */ + } +}; + +static struct platform_driver clk_mt8192_scp_adsp_drv = { + .probe = mtk_clk_simple_probe, + .driver = { + .name = "clk-mt8192-scp_adsp", + .of_match_table = of_match_clk_mt8192_scp_adsp, + }, +}; + +builtin_platform_driver(clk_mt8192_scp_adsp_drv); -- 2.18.0