Received: by 2002:a05:6a10:f3d0:0:0:0:0 with SMTP id a16csp4303417pxv; Mon, 5 Jul 2021 20:10:14 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz8a7GWWzMIccC10m+DfaqxG5F2xvrIt9r32atHQqeGxS7qpg9AiuWx/JDEShaAtOETfWCj X-Received: by 2002:a05:6402:177c:: with SMTP id da28mr791045edb.129.1625541013904; Mon, 05 Jul 2021 20:10:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1625541013; cv=none; d=google.com; s=arc-20160816; b=cqs4l7PwCZG2Uuq6cqxbsB1jjs+uDPmSsbY8SynXzf5dS9bvdrTZUfXot/jiCNad1K 6xlm4suswV8zB/ShtW5xF/9ZjmN8FIpXWfd2Kx+H/vxIfhIEw7BtR1BhpmQiCcEQNMKm +UOFNixTBtjJU+MntYp3CeqJ1uUXStp5Os12QTzzfppk/NOMJ3U1Orwjr/7eyK8UXel0 OxHh6MJ+xPPG8dLNh9qKizOtI+Oe+sMx5j3BTx91u9svpMUMIfYHdCpylRW+rwq7Jp70 Pb15H6GpOfe5w+7aG/EaZBz5KBBCOPGKrQrboqkqjBeNpOpr+VxqqAncvY3kJzZ1AKIL GaKw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=JZUTyb2y4/fgFkYzEjzh+8Ar+82m76/DJImPO4vWfJk=; b=KoYvp/ugp8kPJv8YZgw4lbazwdJU1EUGjLZm8TGEt5VzRG5fRTh4aF/0/qNlbWfK2o hQlovupZFTOc9lNY8UBzj46uENKiCgm/Vpg6Wj9biH8wG22IgDDcus338IBy/hxMaqQx 8Hw6YR50XZAbXzFbBcMnkr9mVCddYUOnTrj/UZt049UggTBcxD8CjjnUgnx0dOslPNKB XPEmJtCMsopupyxTFuGbZ7D48Uubxovrfg0hoE15cr/UpqMynfMBgZNqmWqNsjB9gaGY qtHgrvdI1dUP90/TyQN52h+ou1rnkcMWjd67MUFBS5dJsX5bKTEY+JVzzz1VKtItW5IY FI1w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id v15si1339123edx.168.2021.07.05.20.09.51; Mon, 05 Jul 2021 20:10:13 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229925AbhGFDLY (ORCPT + 99 others); Mon, 5 Jul 2021 23:11:24 -0400 Received: from mail.kernel.org ([198.145.29.99]:39538 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229880AbhGFDLY (ORCPT ); Mon, 5 Jul 2021 23:11:24 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id F0D646197E; Tue, 6 Jul 2021 03:08:43 +0000 (UTC) From: Huacai Chen To: Thomas Gleixner , Marc Zyngier Cc: linux-kernel@vger.kernel.org, Xuefeng Li , Huacai Chen , Jiaxun Yang , Huacai Chen , Chen Zhu Subject: [PATCH 0/9] irqchip: Add LoongArch-related irqchip drivers Date: Tue, 6 Jul 2021 11:08:55 +0800 Message-Id: <20210706030904.1411775-1-chenhuacai@loongson.cn> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. LoongArch includes a reduced 32-bit version (LA32R), a standard 32-bit version (LA32S) and a 64-bit version (LA64). LoongArch use ACPI as its boot protocol LoongArch-specific interrupt controllers (similar to APIC) are already added in the next revision of ACPI Specification (current revision is 6.4). This patchset adds some irqchip drivers for LoongArch, it is preparing to add LoongArch support in mainline kernel, we can see a snapshot here: https://github.com/loongson/linux/tree/loongarch-next Cross-compile tool chain to build kernel: https://github.com/loongson/build-tools/releases Loongson and LoongArch documentations: https://github.com/loongson/LoongArch-Documentation LoongArch-specific interrupt controllers: https://mantis.uefi.org/mantis/view.php?id=2203 Huacai Chen and Chen Zhu(9): irqchip: Adjust Kconfig for Loongson. irqchip/loongson-pch-pic: Improve edge triggered interrupt support. irqchip/loongson-pch-pic: Add ACPI init support. irqchip/loongson-pch-msi: Add ACPI init support. irqchip/loongson-htvec: Add ACPI init support. irqchip/loongson-liointc: Add ACPI init support. irqchip: Add LoongArch CPU interrupt controller support. irqchip: Add Loongson Extended I/O interrupt controller. irqchip: Add Loongson PCH LPC controller support. Signed-off-by: Huacai Chen Signed-off-by: Chen Zhu --- drivers/irqchip/Kconfig | 37 +++- drivers/irqchip/Makefile | 3 + drivers/irqchip/irq-loongarch-cpu.c | 87 ++++++++++ drivers/irqchip/irq-loongson-eiointc.c | 308 +++++++++++++++++++++++++++++++++ drivers/irqchip/irq-loongson-htvec.c | 102 ++++++++++- drivers/irqchip/irq-loongson-liointc.c | 140 ++++++++++++++- drivers/irqchip/irq-loongson-pch-lpc.c | 204 ++++++++++++++++++++++ drivers/irqchip/irq-loongson-pch-msi.c | 69 +++++++- drivers/irqchip/irq-loongson-pch-pic.c | 139 ++++++++++++++- include/linux/cpuhotplug.h | 1 + 10 files changed, 1069 insertions(+), 21 deletions(-) create mode 100644 drivers/irqchip/irq-loongarch-cpu.c create mode 100644 drivers/irqchip/irq-loongson-eiointc.c create mode 100644 drivers/irqchip/irq-loongson-pch-lpc.c -- 2.27.0