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[23.128.96.18]) by mx.google.com with ESMTP id f16si2476424ejq.119.2021.07.08.04.27.02; Thu, 08 Jul 2021 04:27:25 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0220 header.b=Ej1b8LsO; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=REJECT dis=NONE) header.from=marvell.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231720AbhGHL2q (ORCPT + 99 others); Thu, 8 Jul 2021 07:28:46 -0400 Received: from mx0a-0016f401.pphosted.com ([67.231.148.174]:38348 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231707AbhGHL2p (ORCPT ); Thu, 8 Jul 2021 07:28:45 -0400 Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 168BLcBO004916; Thu, 8 Jul 2021 04:25:49 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-type : content-transfer-encoding; s=pfpt0220; bh=GeNAMu0kd78iMzrl8zmafTGHE7bfc5UGTdnB58XifAs=; b=Ej1b8LsO452aiVWRDt4epTan4Z4y1wb+ZkeeNwEzbblEHOTomJLGHi8UEUfKAhb2yOHq n/BHn09p5zDOZQhVSeaOepQQzOhVrPd9fCQETwnYn31gFMoRLvQSs7hdTzEp1ZgWHcvB e4N7SYS4Amyx3xLMfxim1heHhlm8r9P/6Y8EgR2cm1SK9/XBXqL1Qbee/LJrdm1ugvMq CU9fGiDjIYf+ecW2Fp1yOnv3EppByoS83hCh402tton9vpPiVDrrsmtKHslVYCicgP1N h2VgHTwTY7E3RUl08yePMd4kMHPQKteHkbGvMGH6DWnsh0bNyrInciumGs9U9C/M3TpD 4w== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 39nrnu1pax-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 08 Jul 2021 04:25:49 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 8 Jul 2021 04:25:47 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 8 Jul 2021 04:25:47 -0700 Received: from octopus.marvell.com (octopus.marvell.com [10.5.24.3]) by maili.marvell.com (Postfix) with ESMTP id 8DE0D3F7064; Thu, 8 Jul 2021 04:25:43 -0700 (PDT) From: To: , , , , , , , , , , , , CC: , , , , , Konstantin Porotchkin Subject: [PATCH v6 0/5] DTS updates for Marvell Armada CN913x platforms Date: Thu, 8 Jul 2021 14:25:23 +0300 Message-ID: <20210708112528.3254-1-kostap@marvell.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: xOBEOZrK8z6wqLm2RPV_KTJzdRMXEBDq X-Proofpoint-GUID: xOBEOZrK8z6wqLm2RPV_KTJzdRMXEBDq X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391,18.0.790 definitions=2021-07-08_06:2021-07-08,2021-07-08 signatures=0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Konstantin Porotchkin This patch series contains the following changes/fixes: 1. Add support for Armada CN913x Development Board topology "B" 2. Add support for Armada CN913x Reference Design boards (CRB) 3. Fixes the CP11X references in PHY binding document 4. Fixes the NAND paritioninig scheme in DTS eliminating gap between consecutive partitions All above changes are already intergated into Marvell official SDK sources v2: - extract common nodes from DB boards to separate DTSI files - disable eth2 on CRB boards until the required phy mode support is added - mention the switch part ID in CRB board description v3: - do not rename setup A DTS files for DB variants - fix a couple of wrong include names v4: - Rebase on top of Linus master branch (v5.11-rc7) - Remove HS400 timing from CRB AP SDHCI (not supported by connected eMMC) - Add cd-gpio entry to CP0 SDHCI for SD card support - Add a comment to CN9130-CRB patch about the required defconfig changes for supporting the onboard i2c expander - Add Stefan's patch to enable 10G port on CN9130-DB platforms v5: - Extend enablement of 10G port to CN9131-DB platform v6: - Rebased on top of 5.13-rc, merging UTMI settings (requested by Gregory Clement) Grzegorz Jaszczyk (1): Documentation/bindings: phy: update references to cp11x Konstantin Porotchkin (3): arch/arm64/boot/dts/marvell: fix NAND partitioning scheme arm64: dts: cn913x: add device trees for topology B boards arm64: dts: add support for Marvell cn9130-crb platform Stefan Chulski (1): dts: marvell: Enable 10G interfaces on 9130-DB and 9131-DB boards .../bindings/phy/phy-mvebu-comphy.txt | 12 +- arch/arm64/boot/dts/marvell/Makefile | 5 + arch/arm64/boot/dts/marvell/cn9130-crb-A.dts | 38 ++ arch/arm64/boot/dts/marvell/cn9130-crb-B.dts | 46 ++ arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 222 ++++++++++ arch/arm64/boot/dts/marvell/cn9130-db-B.dts | 22 + arch/arm64/boot/dts/marvell/cn9130-db.dts | 403 +---------------- arch/arm64/boot/dts/marvell/cn9130-db.dtsi | 410 ++++++++++++++++++ arch/arm64/boot/dts/marvell/cn9131-db-B.dts | 22 + arch/arm64/boot/dts/marvell/cn9131-db.dts | 197 +-------- arch/arm64/boot/dts/marvell/cn9131-db.dtsi | 206 +++++++++ arch/arm64/boot/dts/marvell/cn9132-db-B.dts | 22 + arch/arm64/boot/dts/marvell/cn9132-db.dts | 218 +--------- arch/arm64/boot/dts/marvell/cn9132-db.dtsi | 227 ++++++++++ 14 files changed, 1244 insertions(+), 806 deletions(-) create mode 100644 arch/arm64/boot/dts/marvell/cn9130-crb-A.dts create mode 100644 arch/arm64/boot/dts/marvell/cn9130-crb-B.dts create mode 100644 arch/arm64/boot/dts/marvell/cn9130-crb.dtsi create mode 100644 arch/arm64/boot/dts/marvell/cn9130-db-B.dts create mode 100644 arch/arm64/boot/dts/marvell/cn9130-db.dtsi create mode 100644 arch/arm64/boot/dts/marvell/cn9131-db-B.dts create mode 100644 arch/arm64/boot/dts/marvell/cn9131-db.dtsi create mode 100644 arch/arm64/boot/dts/marvell/cn9132-db-B.dts create mode 100644 arch/arm64/boot/dts/marvell/cn9132-db.dtsi -- 2.17.1